Data communication apparatus and module using human body
    51.
    发明申请
    Data communication apparatus and module using human body 有权
    数据通信设备和模块使用人体

    公开(公告)号:US20070140120A1

    公开(公告)日:2007-06-21

    申请号:US11637724

    申请日:2006-12-13

    IPC分类号: H04L12/26 H04J3/06

    CPC分类号: H04B13/005 H04L7/00

    摘要: In circumstance of a wearable computing system, in order to effectively transfer data between electronic devices using electric property of human body, minimization, low power, and high-speed are required. Human body data communication apparatus and module using broadband signaling technology is provided to perform high-speed peer-to-peer data communication with a signal electrode and low power. The apparatus and module have a direct coupling interface with a single electrode without an antenna and a sensor, and a transmitter transmitting digital signal without modulation, and a receiver recovering a clock and data by detecting a broadband pulse signal.

    摘要翻译: 在可穿戴式计算系统的情况下,为了在使用人体的电气性能的电子设备之间有效地传输数据,需要最小化,低功率和高速度。 提供使用宽带信令技术的人体数据通信装置和模块,以与信号电极进行高速对等数据通信和低功率。 该装置和模块具有与没有天线和传感器的单个电极的直接耦合接口,以及无调制地发射数字信号的发射器,以及通过检测宽带脉冲信号来恢复时钟和数据的接收器。

    Method of manufacturing a liquid crystal display device
    52.
    发明申请
    Method of manufacturing a liquid crystal display device 有权
    制造液晶显示装置的方法

    公开(公告)号:US20070040973A1

    公开(公告)日:2007-02-22

    申请号:US11498692

    申请日:2006-08-03

    IPC分类号: G02F1/1337

    CPC分类号: G02F1/133753 G02F1/1393

    摘要: A method of manufacturing a liquid crystal display (LCD) device is provided. In the method, a vertical alignment layer having a first area and a second area is formed on a substrate. A first plasma gas is sprayed onto the first area with first spraying conditions under atmospheric pressure. A second plasma gas is sprayed onto the second area with second spraying conditions under atmospheric pressure.

    摘要翻译: 提供一种制造液晶显示(LCD)装置的方法。 在该方法中,在基板上形成具有第一区域和第二区域的垂直取向层。 第一等离子体气体在大气压下的第一喷射条件下喷射到第一区域上。 在大气压下用第二喷射条件将第二等离子体气体喷射到第二区域上。

    Test structures in unused areas of semiconductor integrated circuits and methods for designing the same
    53.
    发明申请
    Test structures in unused areas of semiconductor integrated circuits and methods for designing the same 有权
    半导体集成电路未使用区域的测试结构及其设计方法

    公开(公告)号:US20050272174A1

    公开(公告)日:2005-12-08

    申请号:US10862049

    申请日:2004-06-04

    CPC分类号: H01L22/34 G01R31/2884

    摘要: The present invention is test structures in unused areas of semiconductor integrated circuits and methods for designing the same. In an exemplary aspect of the present invention, a method for placing test structures in a semiconductor integrated circuit includes: (a) detecting a dummy area in a semiconductor integrated circuit, the semiconductor integrated circuit including probe pads on a top metal layer; (b) filling the dummy area with active test cells, the active test cells being connected to one another; and (c) connecting each of the active test cells to the probe pads with a metal line.

    摘要翻译: 本发明是半导体集成电路的未使用区域的测试结构及其设计方法。 在本发明的一个示例性方面,一种用于将测试结构放置在半导体集成电路中的方法包括:(a)检测半导体集成电路中的虚拟区域,所述半导体集成电路包括顶部金属层上的探针焊盘; (b)用活性测试单元填充虚拟区域,活性测试单元彼此连接; 和(c)用金属线将每个活性测试单元与探针垫连接。

    Method for segmentation and volume calculation of white matter, gray matter, and cerebral spinal fluid using magnetic resonance images of the human brain
    54.
    发明授权
    Method for segmentation and volume calculation of white matter, gray matter, and cerebral spinal fluid using magnetic resonance images of the human brain 失效
    使用人脑磁共振图像分割和体积计算白质,灰质和脑脊髓液的方法

    公开(公告)号:US06895107B2

    公开(公告)日:2005-05-17

    申请号:US09902506

    申请日:2001-07-10

    IPC分类号: A61B5/055 G06T5/00 G06K9/00

    摘要: A fully-automated method for segmentation of white matter, gray matter, and cerebral spinal fluid (CSF) and for calculating their respective volumes is disclosed. The technique preferably uses a T2-weighted scan and a proton-density scan. The T2-weighted scans are used to highlight those portion of the brain corresponding to CSF. Thereafter, the proton density images are separated in CSF-containing and CSF-free portions, in accordance with the T2-weighted images. The CSF-free portion is then segmented into white matter and gray matter portions. The CSF-containing portion is further segmented into pure CSF-regions, and regions containing a mixture of gray and white matter and CSF. After CSF is segmented from this mixture, the white and gray matter and again segmented, and the respective volumes of white matter, gray matter, and CSF are calculated. A technique for determining a threshold gray scale value for segmenting the white and gray matter to assist in the visual identification of such regions is also disclosed.

    摘要翻译: 公开了一种用于分割白质,灰质和脑脊髓液(CSF)并用于计算其各自体积的全自动方法。 该技术优选使用T2加权扫描和质子密度扫描。 T2加权扫描用于突出对应于CSF的脑部分。 此后,根据T2加权图像,在含CSF和CSF的部分中分离质子密度图像。 然后将无CSF部分分成白质和灰质部分。 含CSF的部分进一步分成纯的CSF区域,含有灰色和白色物质和CSF的混合物的区域。 在从该混合物中分离CSF后,计算白色和灰色物质并再次分割,并计算白质,灰质和CSF的相应体积。 还公开了一种用于确定用于分割白色和灰色物质以辅助这些区域的视觉识别的阈值灰度值的技术。

    Umos-like gate-controlled thyristor structure for ESD protection
    55.
    发明授权
    Umos-like gate-controlled thyristor structure for ESD protection 有权
    类似Umos的栅极控制晶闸管结构,用于ESD保护

    公开(公告)号:US06555878B2

    公开(公告)日:2003-04-29

    申请号:US10233764

    申请日:2002-09-03

    IPC分类号: H01L2362

    CPC分类号: H01L27/0262 H01L29/7436

    摘要: Described is a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n+ diffusion is formed which straddles the first n-well. The n+ diffusion together with a p+ pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n+ and p+ diffusion are formed in a second n-well. The second n+ and p+ diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n+ diffusion/n-well (cathode), the p-substrate, the second n-well and the second p+/n+ diffusion (anode). A latchup immune circuit is achieved by creating a U-shaped gate structure which is lined with a thick gate oxide—similar to a field oxide—under the poly gate.

    摘要翻译: 描述了具有用于IC器件中的ESD保护电路的U形门(UMOS)的MOS栅极控制SCR(UGSCR)结构,其与浅沟槽隔离(STI)和自对准硅化物(自对准硅)制造技术相兼容 。 UMOS门位于p基板中,并且被两侧的n阱包围。 邻近UMOS门的一侧,形成跨越第一n阱的第一n +扩散。 n +扩散以及旁边扩散的p +拾取器形成SCR(晶闸管)的阴极。 在UMOS门的另一侧附近,在第二n阱中形成第二n +和p +扩散。 第二个n +和p +扩散与UMOS门一起形成SCR的阳极和要保护的电路的输入端。 SCR由第一n +扩散/ n阱(阴极),p衬底,第二n阱和第二p + / n +扩散(阳极)形成。 闭锁免疫电路通过在聚栅下形成一个衬有厚栅极氧化物(类似于场氧化物)的U形门结构来实现。

    Method of forming of high K metallic dielectric layer
    56.
    发明授权
    Method of forming of high K metallic dielectric layer 失效
    形成高K金属介电层的方法

    公开(公告)号:US06492242B1

    公开(公告)日:2002-12-10

    申请号:US09609447

    申请日:2000-07-03

    IPC分类号: H01L2120

    CPC分类号: H01L28/40 H01L21/31683

    摘要: A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures. A second iteration features the exposure of specific regions of an underlying metal layer, to a UV, or to an I line exposure procedure, performed in an oxidizing ambient, with the regions of an underlying metal layer exposed to the UV or I line procedure, via clear regions in an overlying photolithographic plate. This procedure also results in the formation of a high K layer, on a top portion of the underlying metal layer.

    摘要翻译: 在高于周围结构所经历的温度的温度下进行的金属氧化物 - 金属电容器结构的高介电常数(高K)层,其特征在于底层金属层的局部氧化, 已经开发 该方法的第一次迭代的特征在于在氧化环境中使用对底层金属层的局部区域进行的激光烧蚀程序。 激光烧蚀过程仅在激光点产生所需的高温,允许在该温度下产生高K层,而不直接暴露于激光烧蚀过程的半导体衬底上的周围结构保持在较低温度 。 第二次迭代的特征在于在氧化环境中进行的底层金属层的特定区域到UV或I线曝光程序,暴露于UV或I线程序的下面的金属层的区域, 通过覆盖光刻板中的透明区域。 该过程还导致在下面的金属层的顶部上形成高K层。

    UMOS-like gate-controlled thyristor structure for ESD protection
    57.
    发明授权
    UMOS-like gate-controlled thyristor structure for ESD protection 失效
    类似UMOS的门控晶闸管结构,用于ESD保护

    公开(公告)号:US06458632B1

    公开(公告)日:2002-10-01

    申请号:US09814478

    申请日:2001-03-14

    IPC分类号: H01L21332

    CPC分类号: H01L27/0262 H01L29/7436

    摘要: Described is a method of creating a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n+ diffusion is formed which straddles the first n-well. The n+ diffusion together with a p+ pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n+ and p+ diffusion are formed in a second n-well. The second n+ and p+ diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n+ diffusion/n-well (cathode), the p-substrate, the second n-well and the second p+/n+ diffusion (anode). A latchup immune circuit is achieved by creating a U-shaped gate structure which is lined with a thick gate oxide—similar to a field oxide—under the poly gate.

    摘要翻译: 描述了一种用于在IC器件中的用于ESD保护电路的U形栅极(UMOS)的MOS栅极控制SCR(UGSCR)结构的方法,其与浅沟槽隔离(STI)和自对准硅化物(STI)兼容 自杀)制造技术。 UMOS门位于p基板中,并且被两侧的n阱包围。 邻近UMOS门的一侧,形成跨越第一n阱的第一n +扩散。 n +扩散以及旁边扩散的p +拾取器形成SCR(晶闸管)的阴极。 在UMOS门的另一侧附近,在第二n阱中形成第二n +和p +扩散。 第二个n +和p +扩散与UMOS门一起形成SCR的阳极和要保护的电路的输入端。 SCR由第一n +扩散/ n阱(阴极),p衬底,第二n阱和第二p + / n +扩散(阳极)形成。 闭锁免疫电路通过在聚栅下形成一个衬有厚栅极氧化物(类似于场氧化物)的U形门结构来实现。

    Low voltage controllable transient trigger network for ESD protection
    58.
    发明授权
    Low voltage controllable transient trigger network for ESD protection 有权
    低电压可控瞬态触发网络,用于ESD保护

    公开(公告)号:US06275089B1

    公开(公告)日:2001-08-14

    申请号:US09482048

    申请日:2000-01-13

    IPC分类号: H03K508

    CPC分类号: H01L27/0251

    摘要: A transient protection circuit is described which provides electrostatic discharge (ESD) protection for an internal circuit of an IC. The transient protection circuit comprises two Zener diodes connected in series between the input pad and the internal circuit of the IC. A sufficiently large ESD pulse will drive one the two Zener diodes into breakdown mode, thereby reducing the magnitude of the ESD pulse to the remainder of the circuit. Resistive means are paralleled with the Zener diodes to provide a signal path at non-ESD voltages. To help shunt the ESD current away from the internal circuit, PMOS and NMOS transistors are connected in parallel between the positive and the negative voltage supply and their junction is connected to the internal circuit. Negative ESD pulses cause the PMOS transistors to turn on, dumping the ESD energy into the positive voltage supply, while positive ESD pulses cause the NMOS transistors to turn on, dumping the ESD energy into the negative voltage supply. Voltage changes, caused by currents flowing through the resistive means, trigger parasitic SCRs into conduction to provide the bulk of the ESD protection.

    摘要翻译: 描述了为IC的内部电路提供静电放电(ESD)保护的瞬态保护电路。 瞬态保护电路包括串联连接在输入焊盘和IC内部电路之间的两个齐纳二极管。 足够大的ESD脉冲将驱动两个齐纳二极管中的一个进入击穿模式,从而将ESD脉冲的幅度减小到电路的其余部分。 电阻性装置与齐纳二极管并联,以在非ESD电压下提供信号路径。 为了有助于将ESD电流从内部电路分流,PMOS和NMOS晶体管并联连接在正电压和负电源之间,它们的结连接到内部电路。 负ESD脉冲导致PMOS晶体管导通,将ESD能量转储到正电压源中,而正的ESD脉冲使NMOS晶体管导通,将ESD能量转储到负电源。 由电流流过电阻的电流引起的电压变化会将寄生的SCR触发导通,以提供大量的ESD保护。

    Method of fabricating wedge isolation transistors
    59.
    发明授权
    Method of fabricating wedge isolation transistors 失效
    楔形隔离晶体管的制造方法

    公开(公告)号:US06258677B1

    公开(公告)日:2001-07-10

    申请号:US09409875

    申请日:1999-10-01

    IPC分类号: H01L21336

    摘要: A method of fabricating a transistor, comprising the following steps. A silicon semiconductor structure having spaced, raised, wedge-shaped dielectric isolation regions defining an active region there between is provided. Epitaxial silicon is grown over the active area to form an SEG region. A dummy gate is formed over the SEG region. Raised epitaxial silicon layers are grown over the SEG region adjacent the dummy gate. The dummy gate is removed, exposing the interior side walls of the raised epitaxial silicon layers. Sidewall spacers are formed on the exposed sidewalls of the raised epitaxial silicon layers. A gate oxide layer is grown over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. A layer of polysilicon is deposited over the structure and is planarized to form a gate conductor over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. The sidewall spacers are removed. No HDP process trench fill is required to form the STIs and no CMP process is required to planarized the STIs.

    摘要翻译: 一种制造晶体管的方法,包括以下步骤。 提供了具有限定其间的有源区域的具有间隔开的凸起的楔形介电隔离区域的硅半导体结构。 在活性区域上生长外延硅以形成SEG区域。 在SEG区域上形成一个虚拟门。 凸起的外延硅层生长在与虚拟栅极相邻的SEG区域上。 去除虚拟栅极,暴露凸起的外延硅层的内侧壁。 在凸起的外延硅层的暴露的侧壁上形成侧壁间隔物。 栅极氧化物层生长在SEG区域上并且在凸起的外延硅层的侧壁间隔物之间​​。 在该结构上沉积一层多晶硅,并将其平坦化,以在SEG区域和凸出的外延硅层的侧壁间隔物之间​​形成栅极导体。 去除侧壁间隔物。 不需要HDP工艺沟槽填充来形成STI,并且不需要CMP工艺来平坦化STI。

    Hard handoff system for a mobile phone and method therefor
    60.
    发明授权
    Hard handoff system for a mobile phone and method therefor 失效
    手机硬切换系统及其方法

    公开(公告)号:US6128493A

    公开(公告)日:2000-10-03

    申请号:US909478

    申请日:1997-08-11

    申请人: Wan-Jun Song

    发明人: Wan-Jun Song

    CPC分类号: H04W36/38 H04W36/18 H04W36/30

    摘要: Disclosed is a hard handoff system for a mobile phone in a CDMA radio communication system having at least two adjacent first and second cellular service areas, which comprises a first base station for serving the mobile phone in the first cellular service area through one of preset multiple traffic channels, a second base station for serving the mobile phone in the second cellular service area through one of preset multiple traffic channels, and a control station for allocating another one of the multiple traffic channels to the first and second base stations to serve the mobile phone moving from the first to the second cellular service area if the traffic channel serving the first base station is not available for the second base station.

    摘要翻译: 公开了一种具有至少两个相邻的第一和第二蜂窝服务区的CDMA无线电通信系统中的移动电话的硬切换系统,该第一和第二蜂窝服务区包括:第一基站,用于通过预设多个 业务信道,第二基站,用于通过预设的多个业务信道之一为第二蜂窝业务区域中的移动电话服务;以及控制站,用于将多个业务信道中的另一个分配给第一和第二基站,以服务于移动台 如果服务于第一基站的业务信道不可用于第二基站,则电话从第一蜂窝业务区域移动到第二蜂窝业务区域。