摘要:
In circumstance of a wearable computing system, in order to effectively transfer data between electronic devices using electric property of human body, minimization, low power, and high-speed are required. Human body data communication apparatus and module using broadband signaling technology is provided to perform high-speed peer-to-peer data communication with a signal electrode and low power. The apparatus and module have a direct coupling interface with a single electrode without an antenna and a sensor, and a transmitter transmitting digital signal without modulation, and a receiver recovering a clock and data by detecting a broadband pulse signal.
摘要:
A method of manufacturing a liquid crystal display (LCD) device is provided. In the method, a vertical alignment layer having a first area and a second area is formed on a substrate. A first plasma gas is sprayed onto the first area with first spraying conditions under atmospheric pressure. A second plasma gas is sprayed onto the second area with second spraying conditions under atmospheric pressure.
摘要:
The present invention is test structures in unused areas of semiconductor integrated circuits and methods for designing the same. In an exemplary aspect of the present invention, a method for placing test structures in a semiconductor integrated circuit includes: (a) detecting a dummy area in a semiconductor integrated circuit, the semiconductor integrated circuit including probe pads on a top metal layer; (b) filling the dummy area with active test cells, the active test cells being connected to one another; and (c) connecting each of the active test cells to the probe pads with a metal line.
摘要:
A fully-automated method for segmentation of white matter, gray matter, and cerebral spinal fluid (CSF) and for calculating their respective volumes is disclosed. The technique preferably uses a T2-weighted scan and a proton-density scan. The T2-weighted scans are used to highlight those portion of the brain corresponding to CSF. Thereafter, the proton density images are separated in CSF-containing and CSF-free portions, in accordance with the T2-weighted images. The CSF-free portion is then segmented into white matter and gray matter portions. The CSF-containing portion is further segmented into pure CSF-regions, and regions containing a mixture of gray and white matter and CSF. After CSF is segmented from this mixture, the white and gray matter and again segmented, and the respective volumes of white matter, gray matter, and CSF are calculated. A technique for determining a threshold gray scale value for segmenting the white and gray matter to assist in the visual identification of such regions is also disclosed.
摘要:
Described is a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n+ diffusion is formed which straddles the first n-well. The n+ diffusion together with a p+ pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n+ and p+ diffusion are formed in a second n-well. The second n+ and p+ diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n+ diffusion/n-well (cathode), the p-substrate, the second n-well and the second p+/n+ diffusion (anode). A latchup immune circuit is achieved by creating a U-shaped gate structure which is lined with a thick gate oxide—similar to a field oxide—under the poly gate.
摘要:
A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures. A second iteration features the exposure of specific regions of an underlying metal layer, to a UV, or to an I line exposure procedure, performed in an oxidizing ambient, with the regions of an underlying metal layer exposed to the UV or I line procedure, via clear regions in an overlying photolithographic plate. This procedure also results in the formation of a high K layer, on a top portion of the underlying metal layer.
摘要:
Described is a method of creating a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n+ diffusion is formed which straddles the first n-well. The n+ diffusion together with a p+ pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n+ and p+ diffusion are formed in a second n-well. The second n+ and p+ diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n+ diffusion/n-well (cathode), the p-substrate, the second n-well and the second p+/n+ diffusion (anode). A latchup immune circuit is achieved by creating a U-shaped gate structure which is lined with a thick gate oxide—similar to a field oxide—under the poly gate.
摘要:
A transient protection circuit is described which provides electrostatic discharge (ESD) protection for an internal circuit of an IC. The transient protection circuit comprises two Zener diodes connected in series between the input pad and the internal circuit of the IC. A sufficiently large ESD pulse will drive one the two Zener diodes into breakdown mode, thereby reducing the magnitude of the ESD pulse to the remainder of the circuit. Resistive means are paralleled with the Zener diodes to provide a signal path at non-ESD voltages. To help shunt the ESD current away from the internal circuit, PMOS and NMOS transistors are connected in parallel between the positive and the negative voltage supply and their junction is connected to the internal circuit. Negative ESD pulses cause the PMOS transistors to turn on, dumping the ESD energy into the positive voltage supply, while positive ESD pulses cause the NMOS transistors to turn on, dumping the ESD energy into the negative voltage supply. Voltage changes, caused by currents flowing through the resistive means, trigger parasitic SCRs into conduction to provide the bulk of the ESD protection.
摘要:
A method of fabricating a transistor, comprising the following steps. A silicon semiconductor structure having spaced, raised, wedge-shaped dielectric isolation regions defining an active region there between is provided. Epitaxial silicon is grown over the active area to form an SEG region. A dummy gate is formed over the SEG region. Raised epitaxial silicon layers are grown over the SEG region adjacent the dummy gate. The dummy gate is removed, exposing the interior side walls of the raised epitaxial silicon layers. Sidewall spacers are formed on the exposed sidewalls of the raised epitaxial silicon layers. A gate oxide layer is grown over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. A layer of polysilicon is deposited over the structure and is planarized to form a gate conductor over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. The sidewall spacers are removed. No HDP process trench fill is required to form the STIs and no CMP process is required to planarized the STIs.
摘要:
Disclosed is a hard handoff system for a mobile phone in a CDMA radio communication system having at least two adjacent first and second cellular service areas, which comprises a first base station for serving the mobile phone in the first cellular service area through one of preset multiple traffic channels, a second base station for serving the mobile phone in the second cellular service area through one of preset multiple traffic channels, and a control station for allocating another one of the multiple traffic channels to the first and second base stations to serve the mobile phone moving from the first to the second cellular service area if the traffic channel serving the first base station is not available for the second base station.