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    Double patterning friendly lithography method and system
    51.
    发明授权
    Double patterning friendly lithography method and system 有权
    双重图案友好光刻方法和系统

    公开(公告)号：US08245174B2

    公开(公告)日：2012-08-14

    申请号：US12549087

    申请日：2009-08-27

    Applicant: Yi-Kan Cheng ,  Ru-Gun Liu ,  Lee-Chung Lu

    Inventor： Yi-Kan Cheng ,  Ru-Gun Liu ,  Lee-Chung Lu

    IPC: G06F17/50

    CPC classification number: G06F17/5068

    Abstract: A method includes receiving an identification of a plurality of cells to be included in an integrated circuit (IC) layout, including a list of pairs of cells within the plurality of cells to be connected to each other. First routing paths are identified, to connect a maximum number of the pairs of cells using one-dimensional (1-D) routing between cells within those pairs of cells. Second routing paths are selected from a predetermined set of two-dimensional (2-D) routing patterns to connect any of the pairs of cells which cannot be connected by 1-D routing. The first and second routing paths are output to a machine readable storage medium to be read by a control system for controlling a semiconductor fabrication process to fabricate the IC.

    Abstract translation: 一种方法包括接收要包括在集成电路（IC）布局中的多个单元的标识，包括要彼此连接的多个单元格内的单元对对的列表。 识别出第一路由路径，以便在这些小区对内的小区之间使用一维（1-D）路由连接最大数量的小区对。 从预定的二维（2-D）路由模式集合中选择第二路由路径，以连接不能通过1-D路由连接的任何一对小区。 第一和第二路由路径被输出到机器可读存储介质，以由用于控制制造IC的半导体制造工艺的控制系统读取。

    DOUBLE PATTERNING FRIENDLY LITHOGRAPHY METHOD AND SYSTEM
    54.
    发明申请
    DOUBLE PATTERNING FRIENDLY LITHOGRAPHY METHOD AND SYSTEM 有权
    双重图案友好的方法和系统

    公开(公告)号：US20110023002A1

    公开(公告)日：2011-01-27

    申请号：US12549087

    申请日：2009-08-27

    Applicant: Yi-Kan Cheng ,  Ru-Gun Liu ,  Lee-Chung Lu

    Inventor： Yi-Kan Cheng ,  Ru-Gun Liu ,  Lee-Chung Lu

    IPC: G06F17/50

    CPC classification number: G06F17/5068

    Abstract: A method includes receiving an identification of a plurality of cells to be included in an integrated circuit (IC) layout, including a list of pairs of cells within the plurality of cells to be connected to each other. First routing paths are identified, to connect a maximum number of the pairs of cells using one-dimensional (1-D) routing between cells within those pairs of cells. Second routing paths are selected from a predetermined set of two-dimensional (2-D) routing patterns to connect any of the pairs of cells which cannot be connected by 1-D routing. The first and second routing paths are output to a machine readable storage medium to be read by a control system for controlling a semiconductor fabrication process to fabricate the IC.

    Abstract translation: 一种方法包括接收要包括在集成电路（IC）布局中的多个单元的标识，包括要彼此连接的多个单元格内的单元对对的列表。 识别出第一路由路径，以便在这些小区对内的小区之间使用一维（1-D）路由连接最大数量的小区对。 从预定的二维（2-D）路由模式集合中选择第二路由路径，以连接不能通过1-D路由连接的任何一对小区。 第一和第二路由路径被输出到机器可读存储介质，以由用于控制制造IC的半导体制造工艺的控制系统读取。

    Method for smart dummy insertion to reduce run time and dummy count
    55.
    发明授权
    Method for smart dummy insertion to reduce run time and dummy count 有权
    用于智能虚拟插入的方法，以减少运行时间和虚拟计数

    公开(公告)号：US07801717B2

    公开(公告)日：2010-09-21

    申请号：US11625658

    申请日：2007-01-22

    Applicant: Gwan Sin Chang ,  Yi-Kan Cheng ,  Cliff Hou

    Inventor： Gwan Sin Chang ,  Yi-Kan Cheng ,  Cliff Hou

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5068 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method involves providing a circuit pattern, generating a density report for the circuit pattern that identifies a feasible area for dummy insertion, simulating a planarization process with the density report and identifying a hot spot on the circuit pattern, inserting a virtual dummy pattern in the feasible area and adjusting the density report accordingly, and thereafter simulating the planarization process with the adjusted density until the hot spot is eliminated.

    Abstract translation: 一种方法包括提供一种电路图案，产生用于识别用于虚拟插入的可行区域的电路图案的密度报告，用密度报告模拟平面化处理，并识别电路图案上的热点，将虚拟虚拟图案插入到 相应地调整密度报告，然后以调整的密度模拟平坦化处理，直到消除热点。

    Advisory System for Verifying Sensitive Circuits in Chip-Design
    57.
    发明申请
    Advisory System for Verifying Sensitive Circuits in Chip-Design 有权
    芯片设计中验证敏感电路的咨询系统

    公开(公告)号：US20090172617A1

    公开(公告)日：2009-07-02

    申请号：US12054195

    申请日：2008-03-24

    Applicant: Chi-Heng Huang ,  Gary Lin ,  Chu-Fu Chen ,  Yi-Kan Cheng ,  Fu-Lung Hsueh

    Inventor： Chi-Heng Huang ,  Gary Lin ,  Chu-Fu Chen ,  Yi-Kan Cheng ,  Fu-Lung Hsueh

    IPC: G06F17/50

    CPC classification number: G06F17/5036 ,  G06F17/5009

    Abstract: A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design; and a search module. The search module is configured to find sensitive circuits from the potential sensitive circuits; and verify the sensitive circuits.

    Abstract translation: 提供了用于验证集成电路设计的验证系统。 验证系统包括：功能块查找模块，被配置为识别集成电路设计中的潜在敏感电路; 和搜索模块。 搜索模块被配置为从潜在敏感电路中找到敏感电路; 并验证敏感电路。

    Apparatus with detachably connected memory-card type adapter
    58.
    发明授权
    Apparatus with detachably connected memory-card type adapter 失效
    具有可拆卸连接的存储卡型适配器的装置

    公开(公告)号：US07513801B2

    公开(公告)日：2009-04-07

    申请号：US10835351

    申请日：2004-04-28

    Applicant: Tsung-Kan Cheng ,  Forli Wen ,  Tony Chang

    Inventor： Tsung-Kan Cheng ,  Forli Wen ,  Tony Chang

    IPC: H01R12/16

    CPC classification number: H01R31/06 ,  Y10S439/946

    Abstract: An electronic apparatus is provided at one side with an adapting plate, on at least one side surface of which there is provided connecting lines, and a memory-card plug adapter is detachably connected to the apparatus through engagement of a socket provided at a front end of the adapter with the adapting plate on the apparatus. Elastic contact terminals are provided in the socket to electrically connect to the connecting lines on the adapting plate. The apparatus is adapted to plug in any type of memory-card socket provided on a computer through detachable engagement of the adapting plate on the apparatus with one memory-card plug adapter that corresponds to the memory-card socket on the computer.

    Abstract translation: 电子设备在一侧设置有适配板，其至少一个侧表面设置有连接线，并且存储卡插头适配器通过设置在前端的插座的接合而可拆卸地连接到设备 的适配器与设备上的适配板。 弹性接触端子设置在插座中以电连接到适配板上的连接线。 该装置适于插入设在计算机上的任何类型的存储卡插座，通过可拆卸地将适配板与设备上的适配板接合，并具有对应于计算机上的存储卡插槽的一个存储卡插头适配器。

    APPARATUS WITH DETACHABLY CONNECTED MEMORY-CARD TYPE ADAPTER
    59.
    发明申请
    APPARATUS WITH DETACHABLY CONNECTED MEMORY-CARD TYPE ADAPTER 失效
    具有可拆卸连接的存储卡类型适配器的设备

    公开(公告)号：US20090061690A1

    公开(公告)日：2009-03-05

    申请号：US10835351

    申请日：2004-04-28

    Applicant: Tsung-Kan Cheng ,  Forli Wen ,  Tony Chang

    Inventor： Tsung-Kan Cheng ,  Forli Wen ,  Tony Chang

    IPC: H01R12/00

    CPC classification number: H01R31/06 ,  Y10S439/946

    Abstract: An electronic apparatus is provided at one side with an adapting plate, on at least one side surface of which there is provided connecting lines, and a memory-card type adapter is detachably connected to the apparatus through engagement of a socket provided at a front end of the adapter with the adapting plate on the apparatus. Elastic contact terminals are provided in the socket to electrically connect to the connecting lines on the adapting plate. The apparatus is adapted to plug in any type of memory-card socket provided on a computer through detachable engagement of the adapting plate on the apparatus with one memory-card type adapter that corresponds to the memory-card socket on the computer.

    Abstract translation: 电子设备在一侧设置有适配板，其至少一个侧表面设置有连接线，并且存储卡型适配器通过设置在前端的插座的接合而可拆卸地连接到设备 的适配器与设备上的适配板。 弹性接触端子设置在插座中以电连接到适配板上的连接线。 该装置适于插入设置在计算机上的任何类型的存储卡插座，通过适配板在设备上的可拆卸的接合，与一台与计算机上的存储卡插槽对应的存储卡型适配器。

    Method For Smart Dummy Insertion To Reduce Run Time And Dummy Count
    60.
    发明申请
    Method For Smart Dummy Insertion To Reduce Run Time And Dummy Count 有权
    用于智能虚拟插入的方法可减少运行时间和虚拟计数

    公开(公告)号：US20080176343A1

    公开(公告)日：2008-07-24

    申请号：US11625658

    申请日：2007-01-22

    Applicant: Gwan Sin Chang ,  Yi-Kan Cheng ,  Cliff Hou

    Inventor： Gwan Sin Chang ,  Yi-Kan Cheng ,  Cliff Hou

    IPC: H01L21/00

    CPC classification number: G06F17/5072 ,  G06F17/5068 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method involves providing a circuit pattern, generating a density report for the circuit pattern that identifies a feasible area for dummy insertion, simulating a planarization process with the density report and identifying a hot spot on the circuit pattern, inserting a virtual dummy pattern in the feasible area and adjusting the density report accordingly, and thereafter simulating the planarization process with the adjusted density until the hot spot is eliminated.

    Abstract translation: 一种方法包括提供一种电路图案，产生用于识别用于虚拟插入的可行区域的电路图案的密度报告，用密度报告模拟平面化处理，并识别电路图案上的热点，将虚拟虚拟图案插入到 相应地调整密度报告，然后以调整的密度模拟平坦化处理，直到消除热点。

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