公开(公告)号：US20090237978A1

公开(公告)日：2009-09-24

申请号：US12292891

申请日：2008-11-28

Applicant: Kwang Jin Lee ,  Byung Gil Choi

Inventor： Kwang Jin Lee ,  Byung Gil Choi

IPC: G11C7/10 ,  G11C11/21

CPC classification number: G11C8/10 ,  G11C8/12 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C15/00 ,  G11C15/046 ,  G11C2013/0076

Abstract: In one embodiment, the semiconductor device includes a non-volatile memory cell array. Memory cells of the non-volatile memory cell array are resistance based, and each memory cell has a resistance that changes over time after data is written into the memory cell. A write address buffer is configured to store write addresses associated with data being written into the non-volatile memory cell array, and a read unit is configured to perform a read operation to read data from the non-volatile memory cell array. The read unit is configured to control a read current applied to the non-volatile memory cell array during the read operation based on whether a read address matches one of the stored write addresses and at least one indication of settling time of the data being written into the non-volatile memory cell array.

Abstract translation: 在一个实施例中，半导体器件包括非易失性存储单元阵列。 非易失性存储单元阵列的存储单元是基于电阻的，并且每个存储单元具有在将数据写入存储单元之后随时间而改变的电阻。 写地址缓冲器被配置为存储与被写入非易失性存储单元阵列的数据相关联的写地址，并且读单元被配置为执行读操作以从非易失性存储单元阵列读取数据。 读取单元被配置为基于读取地址是否匹配所存储的写入地址之一和写入的数据的建立时间的至少一个指示来控制在读取操作期间施加到非易失性存储器单元阵列的读取电流 非易失性存储单元阵列。

公开(公告)号：US20090235036A1

公开(公告)日：2009-09-17

申请号：US12402006

申请日：2009-03-11

Applicant: Yu-hwan RO ,  Kwang-ho Kim ,  Kwang-jin Lee ,  Joon-yong Choi

Inventor： Yu-hwan RO ,  Kwang-ho Kim ,  Kwang-jin Lee ,  Joon-yong Choi

IPC: G06F12/16 ,  G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0238 ,  G06F12/0223 ,  Y02D10/13

Abstract: A semiconductor memory device includes a memory cell array and the memory cell array includes: a plurality of memory blocks and at least one setting unit. The at least one setting unit stores a location and a size of a boot data storage region within the plurality of memory blocks that stores boot data. The at least one setting units may include a register for setting usage of each memory block as a boot block. The semiconductor device may be a phase-change memory.

Abstract translation: 半导体存储器件包括存储单元阵列，存储单元阵列包括：多个存储块和至少一个设置单元。 所述至少一个设置单元将存储引导数据的多个存储块内的引导数据存储区域的位置和大小存储起来。 至少一个设置单元可以包括用于将每个存储器块的使用设置为引导块的寄存器。 半导体器件可以是相变存储器。

公开(公告)号：US07580295B2

公开(公告)日：2009-08-25

申请号：US11850128

申请日：2007-09-05

Applicant: Kwang-jin Lee ,  Woo-yeong Cho ,  Hye-jin Kim

Inventor： Kwang-jin Lee ,  Woo-yeong Cho ,  Hye-jin Kim

IPC: G11C7/00

CPC classification number: G11C7/1045 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/109 ,  G11C7/22

Abstract: A semiconductor memory device comprises a memory cell array comprising memory cells of a first type. The memory cell array performs write and read operations in response to signals designed for the operation of a memory cell array comprising memory cells of a type other than the first type.

Abstract translation: 半导体存储器件包括包括第一类型存储单元的存储单元阵列。 存储单元阵列响应于设计用于包括除了第一类型之外的类型的存储器单元的存储单元阵列的操作的信号执行写入和读取操作。

公开(公告)号：US07548467B2

公开(公告)日：2009-06-16

申请号：US11955562

申请日：2007-12-13

Applicant: Hye-Jin Kim ,  Kwang-Jin Lee ,  Woo-Yeong Cho ,  Mu-Hui Park

Inventor： Hye-Jin Kim ,  Kwang-Jin Lee ,  Woo-Yeong Cho ,  Mu-Hui Park

IPC: G11C5/14

CPC classification number: G11C13/004 ,  G11C5/147 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C16/30 ,  G11C2013/0054 ,  G11C2213/72

Abstract: There are provided a bias voltage generator, a semiconductor memory device having the bias voltage generator, and a method for generating the bias voltage. The bias voltage generator which generates the bias voltage to control a sensing current supplied to a memory cell for sensing data is characterized in that the bias voltage is output in response to an input voltage being applied, so that a slope of the bias voltage to the input voltage is different in at least two sections divided corresponding to a level of the input voltage.

Abstract translation: 提供了偏置电压发生器，具有偏置电压发生器的半导体存储器件以及用于产生偏置电压的方法。 产生用于控制提供给存储单元的感测电流以感测数据的偏置电压的偏置电压发生器的特征在于，响应于所施加的输入电压而输出偏置电压，使得偏置电压的斜率 至少两个部分的输入电压不同，对应于输入电压的电平。

公开(公告)号：US20090046500A1

公开(公告)日：2009-02-19

申请号：US12187550

申请日：2008-08-07

Applicant: Kwang-Jin LEE ,  Du-Eung KIM ,  Woo-Yeong CHO

Inventor： Kwang-Jin LEE ,  Du-Eung KIM ,  Woo-Yeong CHO

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2211/5622 ,  G11C2211/5641 ,  G11C2213/72 ,  G11C2213/79

Abstract: An apparatus and operating method of a nonvolatile memory device having three-level nonvolatile memory cells is used to store more than one bit of data in a nonvolatile memory cell. In addition, the data can be selectively written through a write-verify operation, thereby improving write operation reliability. The operating method includes providing a memory cell array having first through third nonvolatile memory cells where each memory cell is capable of storing one among first data through third data corresponding to first through third resistance levels, respectively. Each of the resistance levels is different from one another. First and the third data are written to the first and third nonvolatile memory cells, respectively, during a first interval of a write operation. Second data is written to the second nonvolatile memory cell during a second interval of the write operation.

Abstract translation: 使用具有三电平非易失性存储单元的非易失性存储器件的装置和操作方法在非易失性存储单元中存储多于一位的数据。 此外，可以通过写入验证操作来选择性地写入数据，从而提高写入操作的可靠性。 操作方法包括提供具有第一至第三非易失性存储单元的存储单元阵列，其中每个存储单元能够分别在第一数据与第一至第三电阻电平对应的第三数据之间存储一个存储单元。 每个阻力水平彼此不同。 在写入操作的第一间隔期间，分别将第一和第三数据写入第一和第三非易失性存储器单元。 在写入操作的第二间隔期间，将第二数据写入第二非易失性存储单元。

公开(公告)号：US20080305290A1

公开(公告)日：2008-12-11

申请号：US12095294

申请日：2006-11-28

Applicant: Moo Seok Lee ,  Kwang Jin Lee ,  Yong-Cheol Shin

Inventor： Moo Seok Lee ,  Kwang Jin Lee ,  Yong-Cheol Shin

IPC: B32B1/08

CPC classification number: B01D69/08 ,  B01D69/12 ,  B01D2323/02 ,  B01D2325/24 ,  B01D2325/36 ,  B01D2325/40 ,  Y10T428/1372

Abstract: A braid-reinforced composite hollow fiber membrane is disclosed. The braid-reinforced composite hollow fiber membrane comprising a reinforcing material of a tubular braid and a polymer resinous thin film coated on the surface of the tubular braid is characterized in that: the tubular braid comprises multifilaments made of monofilaments having a fineness of 0.01 to 0.4 denier, and the peeling strength of the tubular braid and a polymer resinous thin film coated on the surface thereof is 1 to 10 MPa. In the composite hollow fiber membrane, the fineness of the mono filaments constituting the tubular braid of the reinforcing material is small, that is, 0.01 to 0.4 denier, thus the surface area of the tubular braid contacted with the polymer resinous thin film is increased. Thus, the peeling strength of the tubular braid and the polymer resinous thin film coated on the surface thereof is excellent, and at the same time, the initial wetting property of the composite hollow fiber membrane is excellent, that is, 80 to 120%, due to a capillary tube phenomenon or the like.

Abstract translation: 公开了一种编织增强复合中空纤维膜。 包括管状编织物的增强材料和涂覆在管状编织物表面上的聚合物树脂薄膜的编织增强复合中空纤维膜的特征在于：管状编织物包含由细度为0.01至0.4的单丝制成的复丝 旦尼尔，管状编织物的剥离强度和涂布在其表面上的聚合物树脂薄膜的剥离强度为1〜10MPa。 在复合中空纤维膜中，构成增强材料的管状编织物的单丝的细度小，即0.01〜0.4旦尼尔，因此与聚合物树脂薄膜接触的管状编织物的表面积增加。 因此，管状编织物和其表面上涂覆的聚合物树脂薄膜的剥离强度优异，同时复合中空纤维膜的初始润湿性优异，即80〜120％ 由于毛细管现象等。

公开(公告)号：US20080230466A1

公开(公告)日：2008-09-25

申请号：US10593480

申请日：2005-04-06

Applicant: Kwang Jin Lee ,  Moo Seok Lee ,  Yong Cheol Shin ,  Seong Hak Choi ,  Young Tai Woo

Inventor： Kwang Jin Lee ,  Moo Seok Lee ,  Yong Cheol Shin ,  Seong Hak Choi ,  Young Tai Woo

IPC: B01D63/02

CPC classification number: B01D63/02 ,  B01D61/18 ,  B01D63/026 ,  B01D65/08 ,  B01D2313/06 ,  B01D2313/08 ,  B01D2315/06 ,  B01D2321/185 ,  C02F1/444

Abstract: Disclosed is a submerged hollow fiber membrane module which is easy to expand, has a small installation area, and exhibits excellent contamination prevention and durability. The submerged hollow fiber membrane module comprises: (I) a module body divided into two portions which has a permeated water collection space (5) and a permeated water outlet (3); (II) module support tubes (17) which are vertically connected to the upper and lower ends of the module body; (III) a plate type module header insertion layer which is provided with hollow fiber membrane spaces (10), and is inserted into the module body; (IV) a plate type diffusion layer which is provided with a diffusion port (4) and diffusion tubes (11) and is inserted into the module body subsequent to the module header insertion layer; and (V) module headers which are inserted into the module header insertion layer.

Abstract translation: 公开了一种容易膨胀，安装面积小，防污染性和耐久性优异的浸没式中空纤维膜组件。 浸没式中空纤维膜组件包括：（I）分为两部分的模块体，其具有渗透水收集空间（5）和渗透水出口（3）; （II）模块支撑管（17），其垂直连接到模块主体的上端和下端; （III）板型模块插头层，其设置有中空纤维膜空间（10），并插入模块体内; （IV）板式扩散层，其具有扩散口（4）和扩散管（11），并在模块插入层之后插入模块体内; 和（V）模块插头插入模块插头层。

公开(公告)号：US20080144363A1

公开(公告)日：2008-06-19

申请号：US11953146

申请日：2007-12-10

Applicant: Chang-Soo LEE ,  Hyung-Rok OH ,  Beak-Hyung CHO ,  Kwang-Jin LEE

Inventor： Chang-Soo LEE ,  Hyung-Rok OH ,  Beak-Hyung CHO ,  Kwang-Jin LEE

IPC: G11C11/00 ,  G11C29/00 ,  G11C8/00

CPC classification number: G11C29/08 ,  G11C13/0004

Abstract: A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.

Abstract translation: 公开了一种测试PRAM设备的方法。 该方法通过将设置数据写入第一组存储体并将复位数据写入第二组存储体，同时将输入数据写入多个存储体，通过比较从多个存储体读取的数据执行写操作测试 与相应的输入数据相关，并确定与测试结果相关的故障单元。

公开(公告)号：US20080109700A1

公开(公告)日：2008-05-08

申请号：US11773214

申请日：2007-07-03

Applicant: Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

Inventor： Kwang-Jin Lee ,  Won-Seok Lee ,  Du-Eung Kim

IPC: G06F11/10

CPC classification number: G06F11/1008 ,  G06F11/1076 ,  G11C8/04 ,  G11C8/12

Abstract: A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.

Abstract translation: 半导体存储器件包括存储单元阵列，模式设置电路，奇偶校验数据生成单元和数据错误检测和校正单元。 存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。 模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。 奇偶校验数据生成单元在写入操作期间接收正常写入数据，响应于第二标志信号生成相对于正常写入数据的奇偶校验数据，并输出正常数据和奇偶校验数据。 数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据，响应于第二标志信号检测正常读取数据的错误，当错误为 检测并输出校正的读取数据。

公开(公告)号：US20080084736A1

公开(公告)日：2008-04-10

申请号：US11902704

申请日：2007-09-25

Applicant: Kwang-jin Lee ,  Du-eung Kim ,  Chang-soo Lee ,  Qi Wang

Inventor： Kwang-jin Lee ,  Du-eung Kim ,  Chang-soo Lee ,  Qi Wang

IPC: G11C11/00

CPC classification number: G11C8/16 ,  G11C13/0004 ,  G11C2213/74 ,  G11C2213/79

Abstract: A multi-port phase change random access memory (PRAM) cell, includes a PRAM element including a phase change material, a writing controller configured to operate in correspondence with a writing word line, the writing controller connecting a writing bit line to the PRAM element, and a reading controller configured to operate in correspondence with a reading word line, the reading controller connecting the PRAM element to a reading bit line.

Abstract translation: 多端口相变随机存取存储器（PRAM）单元包括：包括相变材料的PRAM元件，配置成与写入字线对应地进行操作的写入控制器，写入控制器将写入位线连接到PRAM元件 以及读取控制器，被配置为与读取字线对应地操作，读取控制器将PRAM元件连接到读取位线。