公开(公告)号：US20110233653A1

公开(公告)日：2011-09-29

申请号：US13157753

申请日：2011-06-10

申请人： Hak-Sun LEE ,  Kyoung-Sub Shin

发明人： Hak-Sun LEE ,  Kyoung-Sub Shin

IPC分类号： H01L29/792

CPC分类号： H01L27/11573

摘要： A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer formed on the substrate, a charge trapping layer pattern formed on the tunnel insulation layer in the first area of the substrate, a blocking layer pattern formed on the charge trapping layer pattern and a control gate formed on the blocking layer pattern. The control gate has a width substantially smaller than a width of the blocking layer pattern and the width of the control gate is substantially smaller than a width of the charge trapping layer pattern. In addition, an offset is formed between the control gate and the blocking layer pattern such that a spacer is not formed on a sidewall of the control gate.

摘要翻译： 非易失性半导体器件包括在衬底的第一区域中的存储单元，在衬底的第二区域中的低电压晶体管，以及在衬底的第三区域中的高压晶体管。 存储单元包括形成在基板上的隧道绝缘层，形成在基板的第一区域中的隧道绝缘层上的电荷俘获层图案，形成在电荷俘获层图案上的阻挡层图案和形成在基板上的控制栅极 阻挡层图案。 控制栅极的宽度显着小于阻挡层图案的宽度，并且控制栅极的宽度基本上小于电荷俘获层图案的宽度。 此外，在控制栅极和阻挡层图案之间形成偏移，使得在控制栅极的侧壁上未形成间隔物。

公开(公告)号：US20110053327A1

公开(公告)日：2011-03-03

申请号：US12861247

申请日：2010-08-23

申请人： Jun-Ho YOON ,  Kyoung-Sub Shin ,  Sung-Sam Lee ,  Kung-Hyon Nam ,  Hong Cho ,  Joon-Seok Moon

发明人： Jun-Ho YOON ,  Kyoung-Sub Shin ,  Sung-Sam Lee ,  Kung-Hyon Nam ,  Hong Cho ,  Joon-Seok Moon

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/02238 ,  H01L21/3065 ,  H01L29/66621

摘要： Example embodiments relate to a method of forming a recess and a method of manufacturing a semiconductor device having the same. The method includes forming a field region defining an active region in a substrate. The active region extends in a first direction in the substrate. The method further includes forming a preliminary recess extending in a second direction different from the first direction and crossing the active region in the substrate, plasma-oxidizing the substrate to form a sacrificial oxide layer along a surface of the substrate having the preliminary recess, and removing portions of the sacrificial oxide layer and the active region by plasma etching to form a recess having a width larger than a width of the preliminary recess, where an etch rate of the active region is one to two times greater than an etch rate of the sacrificial oxide layer.

摘要翻译： 示例性实施例涉及形成凹部的方法和制造具有该凹部的半导体器件的方法。 该方法包括形成在衬底中限定有源区的场区域。 有源区域在衬底中沿第一方向延伸。 所述方法还包括形成在与所述第一方向不同的第二方向上延伸并且与所述衬底中的有源区交叉的预备凹槽，等离子体氧化所述衬底以沿着具有所述初步凹槽的所述衬底的表面形成牺牲氧化物层，以及 通过等离子体蚀刻去除牺牲氧化物层和有源区的部分以形成具有大于初步凹槽的宽度的宽度的凹部，其中有源区的蚀刻速率是其中的蚀刻速率的一到两倍 牺牲氧化层。

公开(公告)号：US20100173469A1

公开(公告)日：2010-07-08

申请号：US12651781

申请日：2010-01-04

申请人： Hak-Sun Lee ,  Kyoung-Sub Shin ,  Jeong-Dong Choe

发明人： Hak-Sun Lee ,  Kyoung-Sub Shin ,  Jeong-Dong Choe

IPC分类号： H01L21/76

CPC分类号： H01L27/11568

摘要： Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern. A blocking insulating layer is formed that covers the charge trap layer pattern, the isolation layer pattern, and a defined region of the substrate interposed between the charge trap patterns. A gate electrode pattern is formed on the blocking insulating layer to face the charge trap layer pattern. This manufacturing process may reduce charge spreading between unit memory cells and/or may prevent/avoid reduction in the breakdown voltage of the blocking insulating layer.

摘要翻译： 一些方法涉及制造电荷陷阱型非易失性存储器件。 可以形成在衬底中沿第一方向延伸的隔离层图案。 通过使邻近隔离层图案的基板的暴露表面凹陷而在基板中形成凹部单元。 隧道绝缘层和电荷陷阱层依次形成在基板上。 图案化隧道绝缘层和电荷陷阱层，通过蚀刻衬底的限定区域，隔离层图案，隧道绝缘层，隔离层状图案，隔离层状图案，隧道绝缘层， 并且电荷陷阱层直到设置在凹陷单元的底表面上的电荷陷阱层的顶表面与隔离层图案的顶表面对准。 形成了覆盖电荷陷阱层图案，隔离层图案和插入在电荷阱图案之间的基板的限定区域的阻挡绝缘层。 在阻挡绝缘层上形成面对电荷陷阱层图案的栅电极图案。 该制造过程可以减小单元存储单元之间的电荷扩展和/或可以防止/避免阻塞绝缘层的击穿电压的降低。

公开(公告)号：US07728375B2

公开(公告)日：2010-06-01

申请号：US12219358

申请日：2008-07-21

申请人： Kyoung-Sub Shin ,  Cheol-Kyu Lee ,  Sung-il Cho ,  Young-Kyu Cho

发明人： Kyoung-Sub Shin ,  Cheol-Kyu Lee ,  Sung-il Cho ,  Young-Kyu Cho

IPC分类号： H01L27/108

CPC分类号： H01L28/91 ,  H01L27/10855 ,  H01L27/10888

摘要： Example embodiments relate to a semiconductor memory device and a method of forming the semiconductor memory device. The semiconductor memory device may include a first interlayer insulating layer on a semiconductor substrate. A bit line may be arranged in a first direction on the first interlayer insulating layer. A bit line contact pad may be disposed in the first interlayer insulating layer and electrically connected to the bit line. A storage contact pad may be disposed in the first interlayer insulating layer. A top surface of the bit line contact pad may be lower than a top surface of the storage contact pad.

摘要翻译： 示例性实施例涉及半导体存储器件和形成半导体存储器件的方法。 半导体存储器件可以包括半导体衬底上的第一层间绝缘层。 位线可以在第一层间绝缘层上沿第一方向布置。 位线接触焊盘可以设置在第一层间绝缘层中并电连接到位线。 存储接触焊盘可以设置在第一层间绝缘层中。 位线接触焊盘的顶表面可以低于存储触点焊盘的顶表面。

公开(公告)号：US07145140B2

公开(公告)日：2006-12-05

申请号：US10673581

申请日：2003-09-30

申请人： Ji-soo Kim ,  Wan-jae Park ,  Kyoung-sub Shin

发明人： Ji-soo Kim ,  Wan-jae Park ,  Kyoung-sub Shin

IPC分类号： G01N23/225

CPC分类号： H01J37/32935 ,  H01J37/266 ,  H01J2237/004 ,  H01J2237/2594

摘要： In a method for determining the degree of charge-up induced by plasma used for manufacturing a semiconductor device and an apparatus therefor, a predetermined region on a surface of a wafer on which a plasma process has been performed is repeatedly scanned with a primary electron beam. Secondary electrons generated by a reaction between the primary electron beam and the surface of the wafer that are emitted to the outside of the surface of the wafer are collected. The degree of charge-up induced at the surface of the wafer by the plasma used during the plasma process is determined from the change in the amount of collected secondary electrons. Determination as to whether a contact hole is opened or as to the degree of degradation of a gate insulating layer is made based on the degree of charge-up.

摘要翻译： 在用于确定用于制造半导体器件的等离子体引起的充电程度的方法及其装置中，在其上进行了等离子体处理的晶片的表面上的预定区域被一次电子束 。 收集由一次电子束和晶片表面之间的反应产生的二次电子，这些二次电子被发射到晶片表面的外部。 由等离子体工艺中使用的等离子体在晶片表面引起的充电程度由收集的二次电子量的变化确定。 基于充电的程度来确定接触孔是打开还是关于栅极绝缘层的劣化程度。

公开(公告)号：US06777341B2

公开(公告)日：2004-08-17

申请号：US09847289

申请日：2001-05-03

申请人： Kyoung-sub Shin ,  Ji-soo Kim ,  Gyung-jin Min ,  Tae-hyuk Ahn

发明人： Kyoung-sub Shin ,  Ji-soo Kim ,  Gyung-jin Min ,  Tae-hyuk Ahn

IPC分类号： H01L21302

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10888 ,  H01L28/91

摘要： In a method of forming a self-aligned contact, gates are formed on a semiconductor substrate in a striped pattern. Bit lines are formed in a striped pattern that extends cross-wise to the gates. The bit lines are isolated from one another by a first interlayer insulation layer. Next, a second interlayer insulation layer is formed between the bit lines, and a photoresist film pattern is formed on the second interlayer insulation layer. The photoresist film pattern is used for forming contact holes extending between the gates down to conductive pads. The contact holes are filled to form conductive plugs that contact the conductive pads. The photoresist film pattern is formed as a series of stripes which extend parallel to the gates. The stripes of photoresist expose segments of the bit lines and the portions of the second interlayer insulation layer disposed directly above the conductive film pads, thereby securing a sufficient alignment margin, and exposing a large underlying area to be etched in forming the contact holes. To form a semiconductor device, a third interlayer insulation layer, an etch stop layer, an oxide layer and a hard mask layer are formed on the conductive plugs. Next, a second photoresist film pattern is formed on the hard mask layer. The hard mask layer and the oxide layer are etched using the second photoresist film pattern as an etching mask until the etch stop layer is exposed. Second contact holes for use in forming capacitor lower electrodes are formed by sequentially removing the exposed etching stop layer and the exposed third interlayer insulation layer using the hard mask layer as an etching mask, until the second contact holes expose the conductive plugs.

摘要翻译： 在形成自对准接触的方法中，栅极以条纹图案形成在半导体衬底上。 位线以横向延伸到栅极的条纹图案形成。 位线通过第一层间绝缘层彼此隔离。 接着，在位线之间形成第二层间绝缘层，在第二层间绝缘层上形成光致抗蚀剂膜图案。 光致抗蚀剂图案用于形成在栅极之间延伸到导电焊盘的接触孔。 接触孔被填充以形成接触导电垫的导电插塞。 光致抗蚀剂膜图案形成为平行于栅极延伸的一系列条纹。 光致抗蚀剂的条纹将位线的部分和第二层间绝缘层的部分直接设置在导电膜焊盘的正上方，从而确保足够的对准边缘，并且在形成接触孔时暴露待蚀刻的大的下面的区域。 为了形成半导体器件，在导电插塞上形成第三层间绝缘层，蚀刻停止层，氧化物层和硬掩模层。 接下来，在硬掩模层上形成第二光致抗蚀剂图案。 使用第二光致抗蚀剂膜图案作为蚀刻掩模蚀刻硬掩模层和氧化物层，直到暴露出蚀刻停止层。 通过使用硬掩模层作为蚀刻掩模依次去除暴露的蚀刻停止层和暴露的第三层间绝缘层，直到第二接触孔露出导电插塞，形成用于形成电容器下电极的第二接触孔。

公开(公告)号：US06350642B1

公开(公告)日：2002-02-26

申请号：US09885622

申请日：2001-06-20

申请人： Sung-choon Lee ,  Gyung-jin Min ,  Jeong-sic Jeon ,  Kyoung-sub Shin

发明人： Sung-choon Lee ,  Gyung-jin Min ,  Jeong-sic Jeon ,  Kyoung-sub Shin

IPC分类号： H01L218242

CPC分类号： H01L21/76816 ,  H01L21/76897 ,  H01L27/10894

摘要： A method of manufacturing a semiconductor device including various contact studs is provided. According to the method, a plurality of contact holes for various metal contact studs aligned to a bit line, a gate, a semiconductor substrate, or an electrode are formed simultaneously after a capacitor formation process. In this case, an etch stop pattern provided for stopping a selective etching process for forming the contact holes covers the bit line or conductive plugs formed on the semiconductor substrate. The thickness of a first etch stop pattern formed on the bit line or an electrode is similar or substantially the same as a second etch stop pattern formed on conductive plugs. To this end, the method involves selectively removing a capping insulating layer on the bit line for a self aligned contact (SAC) process for forming a conductive pad connected to a capacitor and then depositing a separate etch stop layer. Alternatively, the method may involve reducing the thickness of the capping insulating layer to use it as the first etch stop pattern and forming another second etch stop pattern. In this case, a process of patterning an upper electrode of a capacitor is performed, followed by a process of etching the capping insulating layer.

摘要翻译： 提供一种制造包括各种接触螺柱的半导体器件的方法。 根据该方法，在电容器形成处理之后，同时形成用于与位线对准的多个金属触头柱的多个接触孔，栅极，半导体衬底或电极。 在这种情况下，提供用于停止用于形成接触孔的选择性蚀刻工艺的蚀刻停止图案覆盖形成在半导体衬底上的位线或导电插塞。 形成在位线或电极上的第一蚀刻停止图案的厚度与形成在导电插塞上的第二蚀刻停止图案相似或基本相同。 为此，该方法包括选择性地去除位线上的覆盖绝缘层以进行自对准接触（SAC）工艺，以形成连接到电容器的导电焊盘，然后沉积单独的蚀刻停止层。 或者，该方法可以包括减小封盖绝缘层的厚度以将其用作第一蚀刻停止图案并形成另一个第二蚀刻停止图案。 在这种情况下，进行对电容器的上部电极进行构图的工序，接着进行蚀刻绝缘层的工序。

公开(公告)号：US06342416B1

公开(公告)日：2002-01-29

申请号：US09862305

申请日：2001-05-23

申请人： Ji-soo Kim ,  Jeong-seok Kim ,  Kyoung-sub Shin

发明人： Ji-soo Kim ,  Jeong-seok Kim ,  Kyoung-sub Shin

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

摘要： A semiconductor memory device and manufacturing method, including a bit line connector and a lower electrode connector that respectively connect a bit line and a capacitor lower electrode of the device to active areas of a semiconductor substrate. The connectors are formed using a line-type self-aligned photoresist mask pattern positioned on an interlevel dielectric layer formed on the substrate, which exposes only a portion of the dielectric layer corresponding to a source region and which extends in a direction which a gate electrode extends, to provide a misalignment margin. The bit line connector and the lower electrode connector are respectively formed by one-time mask processes. A contact hole for the bit line connector in a cell area, and a contact hole for a metal wiring plug in a peripheral area are simultaneously formed, alleviating etching burden during subsequent forming of a metal wiring pad.

摘要翻译： 一种半导体存储器件和制造方法，包括分别将器件的位线和电容器下电极连接到半导体衬底的有源区的位线连接器和下电极连接器。 连接器使用位于衬底上形成的层间电介质层上的线型自对准光致抗蚀剂掩模图案形成，该掩模图案仅暴露与源极区对应的介电层的一部分，并且沿栅极电极 延伸，以提供不对准余量。 位线连接器和下电极连接器分别由一次性掩模处理形成。 同时形成用于单元区域中的位线连接器的接触孔和周边区域中的金属布线插塞的接触孔，从而减轻随后形成金属布线板期间的蚀刻负担。