公开(公告)号：US20110053327A1

公开(公告)日：2011-03-03

申请号：US12861247

申请日：2010-08-23

申请人： Jun-Ho YOON ,  Kyoung-Sub Shin ,  Sung-Sam Lee ,  Kung-Hyon Nam ,  Hong Cho ,  Joon-Seok Moon

发明人： Jun-Ho YOON ,  Kyoung-Sub Shin ,  Sung-Sam Lee ,  Kung-Hyon Nam ,  Hong Cho ,  Joon-Seok Moon

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/02238 ,  H01L21/3065 ,  H01L29/66621

摘要： Example embodiments relate to a method of forming a recess and a method of manufacturing a semiconductor device having the same. The method includes forming a field region defining an active region in a substrate. The active region extends in a first direction in the substrate. The method further includes forming a preliminary recess extending in a second direction different from the first direction and crossing the active region in the substrate, plasma-oxidizing the substrate to form a sacrificial oxide layer along a surface of the substrate having the preliminary recess, and removing portions of the sacrificial oxide layer and the active region by plasma etching to form a recess having a width larger than a width of the preliminary recess, where an etch rate of the active region is one to two times greater than an etch rate of the sacrificial oxide layer.

摘要翻译： 示例性实施例涉及形成凹部的方法和制造具有该凹部的半导体器件的方法。 该方法包括形成在衬底中限定有源区的场区域。 有源区域在衬底中沿第一方向延伸。 所述方法还包括形成在与所述第一方向不同的第二方向上延伸并且与所述衬底中的有源区交叉的预备凹槽，等离子体氧化所述衬底以沿着具有所述初步凹槽的所述衬底的表面形成牺牲氧化物层，以及 通过等离子体蚀刻去除牺牲氧化物层和有源区的部分以形成具有大于初步凹槽的宽度的宽度的凹部，其中有源区的蚀刻速率是其中的蚀刻速率的一到两倍 牺牲氧化层。

公开(公告)号：US08426274B2

公开(公告)日：2013-04-23

申请号：US12861247

申请日：2010-08-23

申请人： Jun-Ho Yoon ,  Kyoung-Sub Shin ,  Sung-Sam Lee ,  Kung-Hyon Nam ,  Hong Cho ,  Joon-Seok Moon

发明人： Jun-Ho Yoon ,  Kyoung-Sub Shin ,  Sung-Sam Lee ,  Kung-Hyon Nam ,  Hong Cho ,  Joon-Seok Moon

IPC分类号： H01L21/336 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/02238 ,  H01L21/3065 ,  H01L29/66621

摘要： Example embodiments relate to a method of forming a recess and a method of manufacturing a semiconductor device having the same. The method includes forming a field region defining an active region in a substrate. The active region extends in a first direction in the substrate. The method further includes forming a preliminary recess extending in a second direction different from the first direction and crossing the active region in the substrate, plasma-oxidizing the substrate to form a sacrificial oxide layer along a surface of the substrate having the preliminary recess, and removing portions of the sacrificial oxide layer and the active region by plasma etching to form a recess having a width larger than a width of the preliminary recess, where an etch rate of the active region is one to two times greater than an etch rate of the sacrificial oxide layer.

摘要翻译： 示例性实施例涉及形成凹部的方法和制造具有该凹部的半导体器件的方法。 该方法包括形成在衬底中限定有源区的场区域。 有源区在衬底中沿第一方向延伸。 所述方法还包括形成在与所述第一方向不同的第二方向上延伸并且与所述衬底中的有源区交叉的预备凹槽，等离子体氧化所述衬底以沿着具有所述初步凹槽的所述衬底的表面形成牺牲氧化物层，以及 通过等离子体蚀刻去除牺牲氧化物层和有源区的部分以形成具有大于初步凹槽的宽度的宽度的凹部，其中有源区的蚀刻速率是其中的蚀刻速率的一到两倍 牺牲氧化层。

公开(公告)号：US08420453B2

公开(公告)日：2013-04-16

申请号：US12801074

申请日：2010-05-20

申请人： Jun-Ho Yoon ,  Byeong-Soo Kim ,  Kyoung-Sub Shin ,  Hong Cho ,  Hyung-Yong Kim

发明人： Jun-Ho Yoon ,  Byeong-Soo Kim ,  Kyoung-Sub Shin ,  Hong Cho ,  Hyung-Yong Kim

IPC分类号： H01L21/82

CPC分类号： H01L21/308 ,  H01L21/76229 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/11526

摘要： A method of forming an active region structure includes preparing a semiconductor substrate including a cell array region and a peripheral circuit region, forming preliminary cell active regions in the cell array region of the semiconductor substrate, and forming cell active regions in the preliminary cell active regions and at least one peripheral active region in the peripheral circuit region of the semiconductor substrate, such that the preliminary cell active regions, the cell active regions, and the at least one peripheral active region are integrally formed with the semiconductor substrate and protrude from the semiconductor substrate.

摘要翻译： 形成有源区结构的方法包括制备包括单元阵列区域和外围电路区域的半导体衬底，在半导体衬底的单元阵列区域中形成初级电池活性区域，并在初级电池活性区域中形成电池活性区域 以及半导体衬底的外围电路区域中的至少一个外围有源区域，使得初步电池活性区域，电池活性区域和至少一个外围有源区域与半导体衬底一体地形成并从半导体 基质。

公开(公告)号：US07988874B2

公开(公告)日：2011-08-02

申请号：US12913965

申请日：2010-10-28

申请人： Jeong-Yun Lee ,  Ken Tokashiki ,  Kyoung-Sub Shin ,  Jun-Ho Yoon ,  Hong Cho

发明人： Jeong-Yun Lee ,  Ken Tokashiki ,  Kyoung-Sub Shin ,  Jun-Ho Yoon ,  Hong Cho

IPC分类号： C03C15/00 ,  C03C25/68 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01J37/32165 ,  H01J37/32082 ,  H01J37/32155

摘要： Provided are a method of fabricating a semiconductor device and synchronous pulse plasma etching equipment for the same. The method includes outputting a first radio frequency (RF) power and a control signal and outputting a second RF power. The first RF power is pulse-width modulated to have a first frequency and a first duty ratio, and is applied to a first electrode in a plasma etching chamber. The control signal includes information on a phase of the first RF power. The second RF power is pulse-width modulated to have the first frequency and a second duty ratio smaller than the first duty ratio, is applied to a corresponding second electrode among second electrodes in the plasma etching chamber, and is supplied for a time section in which the first RF power is supplied.

摘要翻译： 提供一种半导体器件和同步脉冲等离子体蚀刻设备的制造方法。 该方法包括输出第一射频（RF）功率和控制信号并输出​​第二RF功率。 第一RF功率被脉冲宽度调制以具有第一频率和第一占空比，并且被施加到等离子体蚀刻室中的第一电极。 控制信号包括关于第一RF功率的相位的信息。 第二RF功率被脉冲宽度调制成具有小于第一占空比的第一频率和第二占空比，被施加到等离子体蚀刻室中的第二电极中的对应的第二电极，并且被提供给 提供第一RF功率。

公开(公告)号：US20110045643A1

公开(公告)日：2011-02-24

申请号：US12801074

申请日：2010-05-20

申请人： Jun-Ho Yoon ,  Byeong-Soo Kim ,  Kyoung-Sub Shin ,  Hong Cho ,  Hyung-Yong Kim

发明人： Jun-Ho Yoon ,  Byeong-Soo Kim ,  Kyoung-Sub Shin ,  Hong Cho ,  Hyung-Yong Kim

IPC分类号： H01L21/70

CPC分类号： H01L21/308 ,  H01L21/76229 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/11526

摘要： A method of forming an active region structure includes preparing a semiconductor substrate including a cell array region and a peripheral circuit region, forming preliminary cell active regions in the cell array region of the semiconductor substrate, and forming cell active regions in the preliminary cell active regions and at least one peripheral active region in the peripheral circuit region of the semiconductor substrate, such that the preliminary cell active regions, the cell active regions, and the at least one peripheral active region are integrally formed with the semiconductor substrate and protrude from the semiconductor substrate.

摘要翻译： 形成有源区结构的方法包括制备包括单元阵列区域和外围电路区域的半导体衬底，在半导体衬底的单元阵列区域中形成初级电池活性区域，并在初级电池活性区域中形成电池活性区域 以及半导体衬底的外围电路区域中的至少一个外围有源区域，使得初步电池活性区域，电池活性区域和至少一个外围有源区域与半导体衬底一体地形成并从半导体 基质。

公开(公告)号：US20110284163A1

公开(公告)日：2011-11-24

申请号：US13086475

申请日：2011-04-14

申请人： Jun-Ho Yoon ,  Kyoung-Sub Shin ,  Woo-Seok Kim ,  Dong-Kwon Kim ,  Hyung-Yong Kim ,  Yong-Ho Jeon

发明人： Jun-Ho Yoon ,  Kyoung-Sub Shin ,  Woo-Seok Kim ,  Dong-Kwon Kim ,  Hyung-Yong Kim ,  Yong-Ho Jeon

IPC分类号： H01L21/00 ,  C23F1/08

CPC分类号： H01L21/67069 ,  H01J37/32935 ,  H01J37/32972

摘要： A plasma processing apparatus includes a chamber for processing a substrate. A plasma generator is provided to generate plasma within the chamber. A window is provided in a sidewall of the chamber, and the window transmits light from the plasma within the chamber. A photocatalytic layer is provided on an inner surface of the window such that the photocatalytic layer is activated as a result of exposure to light from the plasma to decompose a residual product on the inner surface of the window.

摘要翻译： 等离子体处理装置包括用于处理基板的室。 提供等离子体发生器以在腔室内产生等离子体。 窗口设置在室的侧壁中，并且窗口从腔室内的等离子体透射光。 在窗的内表面上提供光催化层，使得光催化层由于暴露于等离子体的光而被激活，从而在窗的内表面上分解残留产物。

公开(公告)号：US20120064709A1

公开(公告)日：2012-03-15

申请号：US13216051

申请日：2011-08-23

申请人： Kyung-Yub JEON ,  Kyoung-Sub Shin ,  Jun-Ho Yoon ,  Je-Woo Han

发明人： Kyung-Yub JEON ,  Kyoung-Sub Shin ,  Jun-Ho Yoon ,  Je-Woo Han

IPC分类号： H01L21/28

CPC分类号： H01L21/28273 ,  H01L21/823456 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/66825

摘要： Provided is a method of forming a semiconductor device. The method may include forming a first insulating layer on a semiconductor substrate. A first polycrystalline silicon layer may be formed on the first insulating layer. A second insulating layer may be formed on the first polycrystalline silicon layer. A second polycrystalline silicon layer may be formed on the second insulating layer. A mask pattern may be formed on the second polycrystalline silicon layer. The second polycrystalline silicon layer may be patterned using the mask pattern as an etch mask to form a second polycrystalline silicon pattern exposing a portion of the second insulating to layer. A sidewall of the second polycrystalline silicon pattern may include a first amorphous region. The first amorphous region may be crystallized by a first recrystallization process. The exposed portion of the second insulating layer may be removed to form a second insulating pattern exposing a portion of the first polycrystalline silicon layer. The exposed portion of the first polycrystalline silicon layer may be removed to form a first polycrystalline silicon pattern exposing a portion of the first insulating layer. The exposed portion of the first insulating layer may be removed to form a first insulating pattern exposing a portion of the semiconductor substrate.

摘要翻译： 提供一种形成半导体器件的方法。 该方法可以包括在半导体衬底上形成第一绝缘层。 可以在第一绝缘层上形成第一多晶硅层。 可以在第一多晶硅层上形成第二绝缘层。 可以在第二绝缘层上形成第二多晶硅层。 可以在第二多晶硅层上形成掩模图案。 可以使用掩模图案作为蚀刻掩模来图案化第二多晶硅层，以形成暴露第二绝缘层的一部分的第二多晶硅图案。 第二多晶硅图案的侧壁可以包括第一非晶区域。 第一非晶区域可以通过第一次重结晶过程结晶。 可以去除第二绝缘层的暴露部分以形成露出第一多晶硅层的一部分的第二绝缘图案。 可以去除第一多晶硅层的暴露部分以形成露出第一绝缘层的一部分的第一多晶硅图案。 可以去除第一绝缘层的暴露部分以形成露出半导体衬底的一部分的第一绝缘图案。

公开(公告)号：US08563371B2

公开(公告)日：2013-10-22

申请号：US13216051

申请日：2011-08-23

申请人： Kyung-Yub Jeon ,  Kyoung-Sub Shin ,  Jun-Ho Yoon ,  Je-Woo Han

发明人： Kyung-Yub Jeon ,  Kyoung-Sub Shin ,  Jun-Ho Yoon ,  Je-Woo Han

IPC分类号： H01L21/84 ,  H01L21/00 ,  H01L21/8238 ,  H01L21/461 ,  H01L21/302

CPC分类号： H01L21/28273 ,  H01L21/823456 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/66825

摘要： Provided is a method of forming a semiconductor device. The method may include forming a first insulating layer on a semiconductor substrate. A first polycrystalline silicon layer may be formed on the first insulating layer. A second insulating layer may be formed on the first polycrystalline silicon layer. A second polycrystalline silicon layer may be formed on the second insulating layer. A mask pattern may be formed on the second polycrystalline silicon layer. The second polycrystalline silicon layer may be patterned using the mask pattern as an etch mask to form a second polycrystalline silicon pattern exposing a portion of the second insulating layer. A sidewall of the second polycrystalline silicon pattern may include a first amorphous region. The first amorphous region may be crystallized by a first recrystallization process. The exposed portion of the second insulating layer may be removed to form a second insulating pattern exposing a portion of the first polycrystalline silicon layer. The exposed portion of the first polycrystalline silicon layer may be removed to form a first polycrystalline silicon pattern exposing a portion of the first insulating layer. The exposed portion of the first insulating layer may be removed to form a first insulating pattern exposing a portion of the semiconductor substrate.

摘要翻译： 提供一种形成半导体器件的方法。 该方法可以包括在半导体衬底上形成第一绝缘层。 可以在第一绝缘层上形成第一多晶硅层。 可以在第一多晶硅层上形成第二绝缘层。 可以在第二绝缘层上形成第二多晶硅层。 可以在第二多晶硅层上形成掩模图案。 可以使用掩模图案作为蚀刻掩模来图案化第二多晶硅层，以形成露出第二绝缘层的一部分的第二多晶硅图案。 第二多晶硅图案的侧壁可以包括第一非晶区域。 第一非晶区域可以通过第一次重结晶过程结晶。 可以去除第二绝缘层的暴露部分以形成露出第一多晶硅层的一部分的第二绝缘图案。 可以去除第一多晶硅层的暴露部分以形成露出第一绝缘层的一部分的第一多晶硅图案。 可以去除第一绝缘层的暴露部分以形成露出半导体衬底的一部分的第一绝缘图案。

公开(公告)号：US09899404B2

公开(公告)日：2018-02-20

申请号：US14957099

申请日：2015-12-02

申请人： Jin-Hyuk Yoo ,  Dae-Hyun Jang ,  Yoo-Chul Kong ,  Kyoung-Sub Shin

发明人： Jin-Hyuk Yoo ,  Dae-Hyun Jang ,  Yoo-Chul Kong ,  Kyoung-Sub Shin

IPC分类号： H01L29/76 ,  H01L27/1157 ,  H01L23/48 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/06

CPC分类号： H01L27/1157 ,  H01L23/48 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.

公开(公告)号：US08669622B2

公开(公告)日：2014-03-11

申请号：US13157753

申请日：2011-06-10

申请人： Hak-Sun Lee ,  Kyoung-Sub Shin

发明人： Hak-Sun Lee ,  Kyoung-Sub Shin

IPC分类号： H01L21/70

CPC分类号： H01L27/11573

摘要： A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer formed on the substrate, a charge trapping layer pattern formed on the tunnel insulation layer in the first area of the substrate, a blocking layer pattern formed on the charge trapping layer pattern and a control gate formed on the blocking layer pattern. The control gate has a width substantially smaller than a width of the blocking layer pattern and the width of the control gate is substantially smaller than a width of the charge trapping layer pattern. In addition, an offset is formed between the control gate and the blocking layer pattern such that a spacer is not formed on a sidewall of the control gate.

摘要翻译： 非易失性半导体器件包括在衬底的第一区域中的存储单元，在衬底的第二区域中的低电压晶体管，以及在衬底的第三区域中的高压晶体管。 存储单元包括形成在基板上的隧道绝缘层，形成在基板的第一区域中的隧道绝缘层上的电荷俘获层图案，形成在电荷俘获层图案上的阻挡层图案和形成在基板上的控制栅极 阻挡层图案。 控制栅极的宽度显着小于阻挡层图案的宽度，并且控制栅极的宽度基本上小于电荷俘获层图案的宽度。 此外，在控制栅极和阻挡层图案之间形成偏移，使得在控制栅极的侧壁上未形成间隔物。