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    Method of forming a self-aligned contact, and method of fabricating a semiconductor device having a self-aligned contact
    1.
    发明授权
    Method of forming a self-aligned contact, and method of fabricating a semiconductor device having a self-aligned contact 有权
    形成自对准接触的方法，以及制造具有自对准接触的半导体器件的方法

    公开(公告)号：US06777341B2

    公开(公告)日：2004-08-17

    申请号：US09847289

    申请日：2001-05-03

    申请人： Kyoung-sub Shin ,  Ji-soo Kim ,  Gyung-jin Min ,  Tae-hyuk Ahn

    发明人： Kyoung-sub Shin ,  Ji-soo Kim ,  Gyung-jin Min ,  Tae-hyuk Ahn

    IPC分类号： H01L21302

    CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10888 ,  H01L28/91

    摘要： In a method of forming a self-aligned contact, gates are formed on a semiconductor substrate in a striped pattern. Bit lines are formed in a striped pattern that extends cross-wise to the gates. The bit lines are isolated from one another by a first interlayer insulation layer. Next, a second interlayer insulation layer is formed between the bit lines, and a photoresist film pattern is formed on the second interlayer insulation layer. The photoresist film pattern is used for forming contact holes extending between the gates down to conductive pads. The contact holes are filled to form conductive plugs that contact the conductive pads. The photoresist film pattern is formed as a series of stripes which extend parallel to the gates. The stripes of photoresist expose segments of the bit lines and the portions of the second interlayer insulation layer disposed directly above the conductive film pads, thereby securing a sufficient alignment margin, and exposing a large underlying area to be etched in forming the contact holes. To form a semiconductor device, a third interlayer insulation layer, an etch stop layer, an oxide layer and a hard mask layer are formed on the conductive plugs. Next, a second photoresist film pattern is formed on the hard mask layer. The hard mask layer and the oxide layer are etched using the second photoresist film pattern as an etching mask until the etch stop layer is exposed. Second contact holes for use in forming capacitor lower electrodes are formed by sequentially removing the exposed etching stop layer and the exposed third interlayer insulation layer using the hard mask layer as an etching mask, until the second contact holes expose the conductive plugs.

    摘要翻译： 在形成自对准接触的方法中，栅极以条纹图案形成在半导体衬底上。 位线以横向延伸到栅极的条纹图案形成。 位线通过第一层间绝缘层彼此隔离。 接着，在位线之间形成第二层间绝缘层，在第二层间绝缘层上形成光致抗蚀剂膜图案。 光致抗蚀剂图案用于形成在栅极之间延伸到导电焊盘的接触孔。 接触孔被填充以形成接触导电垫的导电插塞。 光致抗蚀剂膜图案形成为平行于栅极延伸的一系列条纹。 光致抗蚀剂的条纹将位线的部分和第二层间绝缘层的部分直接设置在导电膜焊盘的正上方，从而确保足够的对准边缘，并且在形成接触孔时暴露待蚀刻的大的下面的区域。 为了形成半导体器件，在导电插塞上形成第三层间绝缘层，蚀刻停止层，氧化物层和硬掩模层。 接下来，在硬掩模层上形成第二光致抗蚀剂图案。 使用第二光致抗蚀剂膜图案作为蚀刻掩模蚀刻硬掩模层和氧化物层，直到暴露出蚀刻停止层。 通过使用硬掩模层作为蚀刻掩模依次去除暴露的蚀刻停止层和暴露的第三层间绝缘层，直到第二接触孔露出导电插塞，形成用于形成电容器下电极的第二接触孔。

    Semiconductor memory device having self-aligned contacts and method of fabricating the same
    2.
    发明授权
    Semiconductor memory device having self-aligned contacts and method of fabricating the same 失效
    具有自对准触点的半导体存储器件及其制造方法

    公开(公告)号：US07132708B2

    公开(公告)日：2006-11-07

    申请号：US11054593

    申请日：2005-02-09

    申请人： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

    发明人： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10888

    摘要： A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, in which a plurality of first spacers are formed along the sidewalls of the gate electrode patterns, a first interdielectric layer formed on the entire surface of a resultant in which the first spacers are formed, a plurality of bit line patterns arranged in parallel on the first interdielectric layer to be perpendicular to the gate electrode patterns, in which a plurality of second spacers are formed along the sidewalls of the bit line patterns, a plurality of contacts for bit lines self-aligned with the first spacers, a second interdielectric layer formed on the entire surface of a resultant in which the second spacers are formed, and a plurality of contacts for storage electrodes simultaneously self-aligned with the second and first spacers.

    摘要翻译： 一种具有自对准触点的半导体存储器件及其制造方法，其特征在于能够防止位线触点和存储电极触点之间的短路，并提高加工余量。 具有自对准触点的半导体存储器件包括平行布置在半导体衬底上的多个栅电极图案，其中多个第一间隔物沿着栅电极图案的侧壁形成，第一绝缘层整体形成 其中形成有第一间隔物的结果的表面，在第一电介质层上平行布置成垂直于栅极电极图案的多个位线图案，其中沿着该位的侧壁形成多个第二间隔物 线图案，用于与第一间隔物自对准的位线的多个触点，形成在其中形成有第二间隔物的结果的整个表面上的第二电介质层和用于存储电极的多个触点同时自对准 与第二和第一间隔物。

    Semiconductor memory device having self-aligned contacts and method of fabricating the same
    4.
    发明授权
    Semiconductor memory device having self-aligned contacts and method of fabricating the same 失效
    具有自对准触点的半导体存储器件及其制造方法

    公开(公告)号：US06885052B2

    公开(公告)日：2005-04-26

    申请号：US09790240

    申请日：2001-02-21

    申请人： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

    发明人： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

    IPC分类号： H01L27/10 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10888

    摘要： A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, in which a plurality of first spacers are formed along the sidewalls of the gate electrode patterns, a first interdielectric layer formed on the entire surface of a resultant in which the first spacers are formed, a plurality of bit line patterns arranged in parallel on the first interdielectric layer to be perpendicular to the gate electrode patterns, in which a plurality of second spacers are formed along the sidewalls of the bit line patterns, a plurality of contacts for bit lines self-aligned with the first spacers, a second interdielectric layer formed on the entire surface of a resultant in which the second spacers are formed, and a plurality of contacts for storage electrodes simultaneously self-aligned with the second and first spacers.

    摘要翻译： 一种具有自对准触点的半导体存储器件及其制造方法，其特征在于能够防止位线触点和存储电极触点之间的短路，并提高加工余量。 具有自对准触点的半导体存储器件包括平行布置在半导体衬底上的多个栅电极图案，其中多个第一间隔物沿着栅电极图案的侧壁形成，第一绝缘层整体形成 其中形成有第一间隔物的结果的表面，在第一电介质层上平行布置成垂直于栅极电极图案的多个位线图案，其中沿着该位的侧壁形成多个第二间隔物 线图案，用于与第一间隔物自对准的位线的多个触点，形成在其中形成有第二间隔物的结果的整个表面上的第二电介质层和用于存储电极的多个触点同时自对准 与第二和第一间隔物。

    Method of and apparatus for manufacturing a semiconductor device using a polysilicon hard mask
    5.
    发明授权
    Method of and apparatus for manufacturing a semiconductor device using a polysilicon hard mask 失效
    使用多晶硅硬掩模制造半导体器件的方法和装置

    公开(公告)号：US06719808B1

    公开(公告)日：2004-04-13

    申请号：US09695068

    申请日：2000-10-25

    申请人： Ji-soo Kim ,  Tae-hyuk Ahn ,  Won-seok Lee ,  Wan-jae Park

    发明人： Ji-soo Kim ,  Tae-hyuk Ahn ,  Won-seok Lee ,  Wan-jae Park

    IPC分类号： H01L21302

    CPC分类号： H01L21/32137 ,  H01L21/31144

    摘要： A method and apparatus for use in manufacturing a semiconductor device strips a polysilicon hard mask without damaging the layer left exposed by openings formed by using the polysilicon hard mask as an etching mask. The method includes forming a polysilicon hard mask in a pattern on a first layer to expose a portion of the first layer, dry etching the exposed portion of the first layer using the polysilicon hard mask as an etching mask to form an opening in the first layer, and thereafter removing the polysilicon hard mask by supplying an etching gas onto the polysilicon hard mask in a direction parallel to the major surface of the semiconductor substrate. The processing apparatus includes a reaction chamber including a spin chuck which supports the semiconductor substrate for rotation, a gas supply unit for supplying a process gas to the reaction chamber, a gas injection unit for injecting the process gas supplied by the gas supply unit into the reaction chamber in a direction parallel to the major surface of the semiconductor substrate, and an exhaust unit for exhausting gases from the reaction chamber.

    摘要翻译： 用于制造半导体器件的方法和装置剥离多晶硅硬掩模，而不会损坏通过使用多晶硅硬掩模形成的开口暴露的层作为蚀刻掩模。 该方法包括在第一层上形成图案中的多晶硅硬掩模以暴露第一层的一部分，使用多晶硅硬掩模作为蚀刻掩模干蚀刻第一层的暴露部分，以在第一层中形成开口 然后通过在多晶硅硬掩模上沿着与半导体基板的主表面平行的方向提供蚀刻气体来除去多晶硅硬掩模。 处理装置包括：反应室，包括支撑旋转用半导体基板的旋转卡盘，向反应室供给处理气体的气体供给单元，将由气体供给单元供给的处理气体注入到 反应室在与半导体基板的主表面平行的方向上，以及用于从反应室排出气体的排气单元。

    Semiconductor memory device having local etch stopper and method of manufacturing the same
    6.
    发明授权
    Semiconductor memory device having local etch stopper and method of manufacturing the same 有权
    具有局部蚀刻停止器的半导体存储器件及其制造方法

    公开(公告)号：US07851354B2

    公开(公告)日：2010-12-14

    申请号：US12267785

    申请日：2008-11-10

    申请人： Jung-woo Seo ,  Jong-seo Hong ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Young-sun Cho

    发明人： Jung-woo Seo ,  Jong-seo Hong ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Young-sun Cho

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76895 ,  H01L21/76837 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

    摘要： A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.

    摘要翻译： 半导体存储器件包括其中限定了单元区域和芯和外围区域的半导体衬底。 该器件还包括形成在半导体衬底中以限定有源区的隔离层，形成在单元区域中的第一栅电极结构和形成在芯和外围区中的第二栅电极结构。 形成在每个栅电极结构和自对准接触焊盘的相应侧上的有源区中的源区和漏区形成在与源区和漏区接触的单元区域中。 在自对准接触焊盘之间的半导体衬底上形成绝缘中间层，并且在电池区域中的自对准接触焊盘之间的绝缘中间层上形成蚀刻阻挡层。

    Method of fabricating a recess channel array transistor using a mask layer with a high etch selectivity with respect to a silicon substrate
    9.
    发明授权
    Method of fabricating a recess channel array transistor using a mask layer with a high etch selectivity with respect to a silicon substrate 有权
    使用相对于硅衬底具有高蚀刻选择性的掩模层来制造凹槽通道阵列晶体管的方法

    公开(公告)号：US07326621B2

    公开(公告)日：2008-02-05

    申请号：US11015366

    申请日：2004-12-16

    申请人： Young-sun Cho ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Ji-hong Kim ,  Hong-Mi Park

    发明人： Young-sun Cho ,  Tae-hyuk Ahn ,  Jeong-sic Jeon ,  Jun-sik Hong ,  Ji-hong Kim ,  Hong-Mi Park

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66621 ,  H01L21/28061 ,  H01L21/28114 ,  H01L21/823487 ,  H01L29/42376

    摘要： A method of fabricating a recess channel array transistor. Using a mask layer pattern having a high etch selectivity with respect to a silicon substrate, the silicon substrate and an isolation insulating layer are etched to form a recess channel trench. After forming a gate insulating layer and a recess gate stack on the recess channel trench, a source and a drain are formed in the silicon substrate adjacent to both sidewalls of the recess gate stack, thereby completing the recess channel array transistor. Because the mask layer pattern having the high etch selectivity with respect to the silicon substrate is used, a depth of the recess channel trench is easily controlled while good etching uniformity of the silicon substrate is obtained.

    摘要翻译： 一种制造凹槽通道阵列晶体管的方法。 使用相对于硅衬底具有高蚀刻选择性的掩模层图案，蚀刻硅衬底和隔离绝缘层以形成凹槽沟道沟槽。 在凹槽沟道沟槽上形成栅极绝缘层和凹槽叠层之后，在与硅栅极叠层的两个侧壁相邻的硅衬底中形成源极和漏极，由此完成凹槽沟道阵列晶体管。 由于使用具有相对于硅衬底的高蚀刻选择性的掩模层图案，所以可以容易地控制凹槽沟槽的深度，同时获得硅衬底的良好蚀刻均匀性。

    Method of manufacturing a semiconductor memory device
    10.
    发明申请
    Method of manufacturing a semiconductor memory device 失效
    制造半导体存储器件的方法

    公开(公告)号：US20050079673A1

    公开(公告)日：2005-04-14

    申请号：US10954835

    申请日：2004-09-29

    申请人： Jung-woo Seo ,  Tae-hyuk Ahn ,  Jeong-sic Jeon

    发明人： Jung-woo Seo ,  Tae-hyuk Ahn ,  Jeong-sic Jeon

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L21/76895 ,  H01L21/76802 ,  H01L21/76831 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

    摘要： Manufacturing a semiconductor memory by first forming a first insulating layer covering a conductive pad. Next forming and pattering a bit line conductive layer and a second insulating layer to expose a part of the first insulating layer. A third insulating layer covering the exposed surfaces of the first insulating layer is formed. Exposing an upper surface of the bit line conductive layer pattern and an upper surface of the third insulating layer. Removing part of the third insulating layer and first insulating layer to expose the conductive pad. Forming a spacer on the side walls of the bit line conductive layer pattern and the first insulating layer. An insulating layer pattern and a second spacer layer are respectively formed on the bit line conductive layer pattern and on a side wall of the first spacer and a conductive plug, which is in contact with the conductive pad is formed.

    摘要翻译： 通过首先形成覆盖导电垫的第一绝缘层来制造半导体存储器。 接下来形成和图案位线导电层和第二绝缘层以暴露第一绝缘层的一部分。 形成覆盖第一绝缘层的暴露表面的第三绝缘层。 露出位线导电层图案的上表面和第三绝缘层的上表面。 去除第三绝缘层和第一绝缘层的一部分以暴露导电焊盘。 在位线导电层图案和第一绝缘层的侧壁上形成间隔物。 分别在位线导电层图案和第一间隔物的侧壁上形成绝缘层图案和第二间隔层，并且形成与导电焊盘接触的导电插塞。