-
公开(公告)号：US12080368B2
公开(公告)日：2024-09-03
申请号：US18221111
申请日：2023-07-12
Applicant: M31 TECHNOLOGY CORPORATION
Inventor： Nan-Chun Lien , Li-Wei Chu , Ting-Wei Chang
CPC classification number: G11C5/025 , G11C7/1057 , G11C7/1084
Abstract: A circuit module with improved line load, may comprise a first line, a first switch, a second line, a second switch and a second driver. The first switch may be on and off to conduct and stop conducting between the first line and a first node. The second switch may be on and off to conduct and stop conducting between the second line and the first node. The second driver, coupled to the second line, may be enabled to drive the second line according to a voltage of a second node, and may be disabled to stop driving the second line. The voltage of the second node may be controlled by a voltage of the first node. When the first switch is on, the second switch may be off. When the second switch is off, the second driver may be enabled.
-
公开(公告)号：US11935581B2
公开(公告)日：2024-03-19
申请号：US17828071
申请日：2022-05-31
Applicant: M31 TECHNOLOGY CORPORATION
Inventor： Li-Wei Chu , Nan-Chun Lien
IPC: G11C11/34 , G11C11/4074 , G11C11/4076 , G11C11/408 , G11C11/4091 , G11C11/4096
CPC classification number: G11C11/4091 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4096
Abstract: A circuit module with reliable margin configuration, may include a main circuit, a first auxiliary circuit and a second auxiliary circuit. When the first auxiliary circuit is on, the second auxiliary circuit may be on or off according to whether a control signal is of a first level or a second level. When the first auxiliary circuit and the second auxiliary circuit are both on, the first auxiliary circuit and the second auxiliary circuit may jointly cause an operation parameter of the main circuit to be a first value. When the first auxiliary circuit is on and the second auxiliary circuit is off, the first auxiliary circuit may cause the operation parameter to be a second value. An operation margin of the main circuit may cover a range between the first value and the second value.
-
公开(公告)号：US20230335188A1
公开(公告)日：2023-10-19
申请号：US18129196
申请日：2023-03-31
Applicant: M31 TECHNOLOGY CORPORATION
Inventor： Po-Yu WU , Hao-I YANG , Nan-Chun LIEN
IPC: G11C11/419
CPC classification number: G11C11/419 , G11C11/412
Abstract: A memory module with improved timing adaptivity of sensing amplification, comprises at least one sensing amplifier, a tracking word line, a tracking bit line and a pulse-width controller. The tracking word line comprises a front node and an end node. Each said sensing amplifier is enabled/disabled when an enabling signal is activated/deactivated. The pulse-width controller is coupled to the tracking bit line, the front node and the end node. When a voltage of the tracking bit line changes to a predetermined voltage, the pulse-width controller activates the enabling signal, and causes a voltage of the front node to change. When the voltage of the front node changes, the tracking word line causes a voltage of the end node to change after a first delay time. When the voltage of the end node changes, the pulse-width controller deactivates the enabling signal after a second delay time.
-
54.发明申请公开(公告)号：US20230135657A1
公开(公告)日：2023-05-04
申请号：US18146789
申请日：2022-12-27
Applicant: M31 TECHNOLOGY CORPORATION
Inventor： CHING-HSIANG CHANG , CHIH-CHIEH YAO , CHUN-HSIANG LAI
Abstract: A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.
-
公开(公告)号：US20220399052A1
公开(公告)日：2022-12-15
申请号：US17828071
申请日：2022-05-31
Applicant: M31 TECHNOLOGY CORPORATION
Inventor： Li-Wei CHU , Nan-Chun LIEN
IPC: G11C11/4091 , G11C11/4096 , G11C11/4074 , G11C11/4076 , G11C11/408
Abstract: A circuit module with reliable margin configuration, may include a main circuit, a first auxiliary circuit and a second auxiliary circuit. When the first auxiliary circuit is on, the second auxiliary circuit may be on or off according to whether a control signal is of a first level or a second level. When the first auxiliary circuit and the second auxiliary circuit are both on, the first auxiliary circuit and the second auxiliary circuit may jointly cause an operation parameter of the main circuit to be a first value. When the first auxiliary circuit is on and the second auxiliary circuit is off, the first auxiliary circuit may cause the operation parameter to be a second value. An operation margin of the main circuit may cover a range between the first value and the second value.
-
Patent Agency Ranking
公开(公告)号：US11411574B2
公开(公告)日：2022-08-09
申请号：US17215428
申请日：2021-03-29
Applicant: M31 TECHNOLOGY CORPORATION
Inventor： Cheng-Liang Hung , Ching-Hsiang Chang
Abstract: A clock and data recovery circuit includes a phase detector (PD), a phase frequency detector (PFD), a multiplexer circuit, a conversion stage and an oscillator. The PD detects a difference in phase between a data signal and an oscillating signal to generate a first set of error signals. The PFD detects a difference in phase and frequency between a reference clock signal and the oscillating signal to generate a second set of error signals. The multiplexer circuit selectively outputs the first set of error signals or the second set of error signals as a third set of error signals according to a selection signal. The conversion stage determines a set of gains according to the selection signal, and converts the third set of error signals with the set of gains to generate a set of input signals. The oscillator generates the oscillating signal according to the set of input signals.
-
57.发明申请公开(公告)号：US20210399733A1
公开(公告)日：2021-12-23
申请号：US17355180
申请日：2021-06-23
Applicant: M31 TECHNOLOGY CORPORATION
Inventor： CHING-HSIANG CHANG , YU-HSUN CHIEN
Abstract: A phase-locked loop circuit includes a phase frequency detector (PHD) circuit, a digital code generator circuit, a frequency divider and an oscillator circuit. The PFD circuit is configured to detect a difference in phase and frequency between a reference clock and a feedback clock to generate a first control signal and a second control signal. The digital code generator circuit is configured to process the second control signal to generate a digital code. The frequency divider is configured to receive an output clock to generate the feedback clock. The oscillator circuit is configured to generate the output clock according to the first control signal and the digital code. A frequency of the output clock is determined according to a first control parameter and a second control parameter of different types. The first and second control parameters are adjusted in response to the first control signal and the digital code respectively.
-
58.发明申请公开(公告)号：US20210399732A1
公开(公告)日：2021-12-23
申请号：US17355178
申请日：2021-06-23
Applicant: M31 TECHNOLOGY CORPORATION
Inventor： GUO-HAU LEE , HUAI-TE WANG , CHENG-LIANG HUNG
Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.
-
公开(公告)号：US11012087B2
公开(公告)日：2021-05-18
申请号：US16701088
申请日：2019-12-02
Applicant: M31 TECHNOLOGY CORPORATION
Inventor： Ching-Hsiang Chang , Yueh-Chuan Lu
Abstract: A physical layer circuit at a transmitter includes an encoding chain and a plurality of flip-flops. The encoding chain, including encoding units coupled in series, is configured to encode a plurality of symbols to generate a plurality of first wire states. The encoding units are arranged to receive the symbols respectively, and convert respective symbol values of the symbols to the first wire states respectively. A first encoding unit is configured to convert a symbol value of a corresponding symbol according to a second wire state provided by a second encoding unit. The flip-flops are arranged to receive and output the first wire states according to a clock signal, respectively. One of the flip-flops is coupled between the first encoding unit and the second encoding unit. The second wire state provided by the second encoding unit is sent to the first encoding unit through the one of the flip-flops.
-
公开(公告)号：US10804884B1
公开(公告)日：2020-10-13
申请号：US16749366
申请日：2020-01-22
Applicant: M31 TECHNOLOGY CORPORATION
Inventor： Ming-Yen Tsai , Chun-Hsiang Lai
IPC: H03L5/00 , H03K3/037 , H03K19/003 , H03K19/0185
Abstract: A level shifter includes a latch circuit, an input stage, a driver stage and a control circuit. The latch circuit is configured to generate an output signal according to a signal level at a first drive node and a signal level at a second drive node. The input stage is configured to receive an input signal to adjust a signal level at a connection node. The driver stage is configured to drive the first drive node by coupling the connection node to the first drive node according to a set of control signals. The control circuit is coupled to the input stage and the driver stage. The control circuit is configured to control the driver stage to couple the connection node to the first drive node by adjusting a signal level of each control signal in the set of control signals during a level transition of the input signal.
-
-
-
-
-
-
-
-
-
Search Results
99
records
(took 0.026 seconds)
