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76 条记录 (耗时 0.035 秒)

    Multi-write coding of non-volatile memories
    52.
    发明授权
    Multi-write coding of non-volatile memories 有权
    非易失性存储器的多写编码

    公开(公告)号：US08176234B2

    公开(公告)日：2012-05-08

    申请号：US12631470

    申请日：2009-12-04

    申请人： Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano

    发明人： Michele M. Franceschini ,  Ashish Jagmohan ,  Luis A. Lastras-Montano

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246 ,  G06F2212/401 ,  G11C11/5621 ,  G11C16/3418 ,  G11C16/349

    摘要： Multi-write coding of non-volatile memories including a method that receives write data, and a write address of a memory page. The memory page is in either an erased state or a previously written state. If the memory page is in the erased state: selecting a first codeword from a code such that the first codeword encodes the write data and is consistent with a target set of distributions of electrical charge levels in the memory page; and writing the first codeword to the memory page. If the memory page is in the previously written state: selecting a coset from a linear code such that the coset encodes the write data and includes one or more words that are consistent with previously written content of the memory page; selecting a subsequent codeword from the one or more words in the coset; and writing the subsequent codeword to the memory page.

    摘要翻译： 包括接收写入数据的方法的非易失性存储器的多写入编码以及存储器页面的写入地址。 存储器页面处于擦除状态或先前写入的状态。 如果存储器页面处于擦除状态：从代码中选择第一码字，使得第一码字对写入数据进行编码，并与存储器页面中的电荷电平分布的目标集合一致; 以及将所述第一码字写入所述存储器页。 如果存储器页面处于先前写入的状态：从线性代码选择陪集，使得陪集对编写数据进行编码并且包括与存储器页面的先前写入的内容一致的一个或多个单词; 从陪集中的一个或多个单词中选择随后的码字; 以及将所述后续码字写入所述存储器页面。

    Memory reading method for resistance drift mitigation
    53.
    发明授权
    Memory reading method for resistance drift mitigation 有权
    电阻漂移缓解的记忆读取方法

    公开(公告)号：US08144508B2

    公开(公告)日：2012-03-27

    申请号：US12984682

    申请日：2011-01-05

    申请人： Michele M. Franceschini ,  John P. Karidis ,  Luis A. Lastras

    发明人： Michele M. Franceschini ,  John P. Karidis ,  Luis A. Lastras

    IPC分类号： G11C11/00

    CPC分类号： G11C13/004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0033 ,  G11C2013/0052

    摘要： Techniques for reading phase change memory that mitigate resistance drift. One contemplated method includes apply a plurality of electrical input signals to the memory cell. The method includes measuring a plurality of electrical output signals from the memory cell resulting from the plurality of electrical input signals. The method includes calculating an invariant component of the plurality of electrical output signals dependent on the configuration of amorphous material in the memory cell. The method also includes determining a memory state of the memory cell based on the invariant component. In one embodiment of the invention, the method further includes mapping the plurality of electrical output signals to a measurements region of a plurality of measurements regions. The measurements regions correspond to memory states of the memory cell.

    摘要翻译： 读取相变存储器的技术，减轻电阻漂移。 一种预期的方法包括将多个电输入信号应用于存储器单元。 该方法包括从多个电输入信号测量来自存储器单元的多个电输出信号。 该方法包括根据存储单元中非晶材料的配置来计算多个电输出信号的不变分量。 该方法还包括基于不变分量来确定存储器单元的存储器状态。 在本发明的一个实施例中，该方法还包括将多个电输出信号映射到多个测量区域的测量区域。 测量区域对应于存储器单元的存储器状态。

    PLANAR PHASE-CHANGE MEMORY CELL WITH PARALLEL ELECTRICAL PATHS
    55.
    发明申请
    PLANAR PHASE-CHANGE MEMORY CELL WITH PARALLEL ELECTRICAL PATHS 有权
    平面相变存储器单元并联电路

    公开(公告)号：US20110317481A1

    公开(公告)日：2011-12-29

    申请号：US12823924

    申请日：2010-06-25

    申请人： Michele M. Franceschini ,  John P. Karidis

    发明人： Michele M. Franceschini ,  John P. Karidis

    IPC分类号： G11C11/00 ,  G06F17/50 ,  H01L45/00

    CPC分类号： G11C8/10 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0083 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/1675

    摘要： A planar phase change memory cell with parallel electrical paths. The memory cell includes a first conductive electrode region having a length greater than its width and an axis aligned with the length. The memory cell also includes a second conductive electrode region having an edge oriented at an angle to the axis of the first conductive electrode region. The memory cell further includes an insulator region providing a lateral separation distance between an end of the first conductive electrode region and the edge of the second conductive electrode region, the insulator region including at least part of an insulator film and the lateral separation distance is responsive to the thickness of the insulator film.

    摘要翻译： 具有并联电路径的平面相变存储单元。 存储单元包括具有大于其宽度的长度的第一导电电极区域和与该长度对准的轴线。 存储单元还包括具有与第一导电电极区域的轴成一定角度的边缘的第二导电电极区域。 存储单元还包括绝​​缘体区域，其在第一导电电极区域的端部和第二导电电极区域的边缘之间提供横向间隔距离，绝缘体区域包括绝缘膜的至少一部分，并且横向间隔距离是响应的 到绝缘膜的厚度。

    ITERATIVE WRITE PAUSING TECHNIQUES TO IMPROVE READ LATENCY OF MEMORY SYSTEMS
    57.
    发明申请
    ITERATIVE WRITE PAUSING TECHNIQUES TO IMPROVE READ LATENCY OF MEMORY SYSTEMS 有权
    迭代写暂停技术来改善读取存储器系统的延迟

    公开(公告)号：US20110026318A1

    公开(公告)日：2011-02-03

    申请号：US12533548

    申请日：2009-07-31

    申请人： Michele M. Franceschini ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi ,  Vijayalakshmi Srinivasan

    发明人： Michele M. Franceschini ,  Luis A. Lastras-Montano ,  Moinuddin K. Qureshi ,  Vijayalakshmi Srinivasan

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G06F13/1642 ,  G06F13/161

    摘要： Iterative write pausing techniques to improve read latency of memory systems including memory systems with phase change memory (PCM) devices. A PCM device includes a plurality of memory locations and a mechanism for executing an iterative write to one or more of the memory locations in response to receiving a write command that includes data to be written. The executing includes initiating the iterative write, updating a state of the iterative write, pausing the iterative write including saving the state in response to receiving a pause command, and resuming the iterative write in response to receiving a resume command. The resuming is responsive to the saved state and to the data to be written.

    摘要翻译： 迭代写暂停技术，以提高内存系统（包括具有相变存储器（PCM）设备的存储器系统）的读取延迟。 PCM设备包括多个存储器位置和用于响应于接收到包括要写入的数据的写入命令而执行对一个或多个存储器位置的迭代写入的机制。 执行包括启动迭代写入，更新迭代写入的状态，暂停迭代写入，包括响应于接收到暂停命令而保存状态，以及响应于接收到恢复命令恢复迭代写入。 恢复响应于保存的状态和要写入的数据。

    Solid-state storage management
    59.
    发明授权
    Solid-state storage management 有权

    公开(公告)号：US09740439B2

    公开(公告)日：2017-08-22

    申请号：US13336385

    申请日：2011-12-23

    申请人： Michele M. Franceschini ,  Ashish Jagmohan

    发明人： Michele M. Franceschini ,  Ashish Jagmohan

    IPC分类号： G06F3/06 ,  G06F12/02

    CPC分类号： G06F3/0688 ,  G06F3/0601 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0652 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7211

    摘要： Solid-state storage management for a system that includes a main board and a solid-state storage board separate from the main board is provided. The solid-state storage board includes a solid-state memory device and solid-state storage devices. The system is configured to perform a method that includes a correspondence being established, by a software module located on the main board, between a first logical address and a first physical address on the solid-state storage devices. The correspondence between the first logical address and the first physical address is stored in a location on the solid-state memory device. The method also includes translating the first logical address into the first physical address. The translating is performed by an address translator module located on the solid-state storage board and is based on the previously established correspondence between the first logical address and the first physical address.