公开(公告)号：US20250140753A1

公开(公告)日：2025-05-01

申请号：US18920749

申请日：2024-10-18

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Kunal R. Parekh ,  Akshay N. Singh ,  Eiichi Nakano

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18

Abstract: A semiconductor device assembly is disclosed. The semiconductor device assembly includes a first semiconductor die and second semiconductor dies and an additional semiconductor component coupled with the logic die. Dielectric peripheral material is disposed along sidewalls of the first die and extends beyond a first footprint of the first die. A gap fill material is disposed at the first die and at the dielectric peripheral material beyond a second footprint of the second semiconductor dies and a third footprint of the additional semiconductor component such that the gap fill material at least partially surrounds the second semiconductor dies and the additional semiconductor component.

公开(公告)号：US20250140306A1

公开(公告)日：2025-05-01

申请号：US19011091

申请日：2025-01-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christopher G. Wieduwilt ,  John P. Behrend

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4093

Abstract: Apparatuses and methods for controlling sense amplifier operation are described. An example method includes providing a control signal having a first high logic level voltage to activate isolation switches of a sense amplifier. The control signal transitions from the first high logic level voltage to an inactive voltage to deactivate the isolation switches of the sense amplifier before accessing a memory cell. The control signal is provided having the first high logic level voltage to activate the isolation switches of the sense amplifier after accessing the memory cell. The control signal is increased from the first high logic level voltage to a second high logic level voltage.

公开(公告)号：US20250138734A1

公开(公告)日：2025-05-01

申请号：US19010977

申请日：2025-01-06

Applicant: Micron Technology, Inc.

Inventor： Michael Burk

IPC: G06F3/06

Abstract: The present disclosure includes apparatuses, methods, and systems for partitioning system data from user data in memory. In an example, a method can include receiving system data at a memory, assigning the system data a first address within a first range of memory addresses, storing the system data in a first portion of the memory operated with a first set of trim settings in response to the system data having the first address within the first range of memory addresses, receiving user data, assigning the user data a second address within a second range of memory addresses, and storing the user data in a second portion of the memory operated with a second set of trim settings in response to the user having the second address within the second range of addresses.

公开(公告)号：US12288563B2

公开(公告)日：2025-04-29

申请号：US17460122

申请日：2021-08-27

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale

IPC: G10L17/18 ,  G06F17/16 ,  G06N3/08 ,  G06N3/10 ,  G10L17/00 ,  G10L17/04 ,  G10L25/30 ,  G10L25/63 ,  H04R1/04 ,  H04R3/00 ,  H04R17/02

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, a microphone may be configured to execute instructions with matrix operands and configured with: a transducer to convert sound waves to electrical signals; an analog to digital converter to generate audio data according to the electrical signals; random access memory to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; and a controller to store the audio data in the random access memory as an input to the Artificial Neural Network. The Deep Learning Accelerator can execute the instructions to generate an output of the Artificial Neural Network, which may be provided as the primary output of the microphone to a computer system, such as a voice-based digital assistant.

公开(公告)号：US20250133724A1

公开(公告)日：2025-04-24

申请号：US18777342

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege

IPC: H10B12/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: A variety of applications can include a memory device having an array of memory cells arranged as hexagonal cells, with each of the memory cells having a gate-all-around (GAA) transistor coupled to a capacitor. Digit lines to the memory cells can be arranged angled relative to the set of access lines at an angle different from ninety degrees. Digit shield lines can be structured between adjacent digit lines. The memory device can be arranged in a wafer-to-wafer interconnect architecture with the array on an array wafer connected to and below a control circuitry wafer in a circuit over array architecture.

公开(公告)号：US20250133721A1

公开(公告)日：2025-04-24

申请号：US18777695

申请日：2024-07-19

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Efe Sinan Ege ,  Haitao Liu

IPC: H10B12/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A variety of applications can include a memory device having an array of memory cells arranged as hexagonal cells, with each of the memory cells having a gate-all-around (GAA) transistor coupled to a capacitor. An access line can be coupled to gates of a first set of multiple GAA transistors of the memory cells. A digit line can be coupled to a second set of multiple GAA transistors of the memory cells, where the digit line is wrapped on a sidewall of an active area of each GAA transistor of the second set. Additional devices and methods are disclosed.

公开(公告)号：US20250133720A1

公开(公告)日：2025-04-24

申请号：US18777396

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Efe Sinan Ege

IPC: H10B12/00 ,  G11C11/4091 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A variety of applications can include a memory device having an array of memory cells arranged as hexagonal cells, with each of the memory cells having a gate-all-around (GAA) transistor coupled to a capacitor. An access line can be coupled to gates of a first set of multiple GAA transistors of the memory cells. A digit line can be coupled to a second set of multiple GAA transistors of the memory cells, where the digit line is separated from an adjacent digit line by an airgap. Additional devices and methods are disclosed.

公开(公告)号：US20250132267A1

公开(公告)日：2025-04-24

申请号：US18999321

申请日：2024-12-23

Applicant: Micron Technology, Inc.

Inventor： Andrew Zhe Wei Ong ,  Liu Ziyan ,  Soo Ting Helen Yee ,  Qitao Fu

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B43/27

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers of respective memory cells and control gates, the tier located one over another over a substrate, the control gates including a control gate closest to the substrate, the control gates including respective portions forming a staircase structure; conductive contacts contacting the control gates at a location of the staircase structure, the conductive contacts including a conductive contact contacting the control gate; a dielectric structure located on sidewalls of the control gates; and support structures adjacent the conductive contacts and having lengths extending vertically from the substrate, the support structures including a support structure closest to the conductive contact, the support structure located at a distance from an edge of the dielectric structure, wherein a ratio of a width of the support structure over the distance is ranging from 1.6 to 2.0.

公开(公告)号：US20250132240A1

公开(公告)日：2025-04-24

申请号：US18781338

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Faxing CHE ,  Hong Wan NG

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H10B80/00

Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, semiconductor device assembly includes a first redistribution layer and a second redistribution layer, a first semiconductor die disposed between the first redistribution layer and the second redistribution layer and connected to the first redistribution layer, and a second semiconductor die disposed between the first redistribution layer and the second redistribution layer and connected to the second redistribution layer. The first semiconductor die may have an active surface and a back surface opposite the active surface of the first semiconductor die. The second semiconductor die may have an active surface and a back surface opposite the active surface of the second semiconductor die. The second semiconductor die may be stacked on the first semiconductor die with the back surface of the second semiconductor die facing the back surface of the first semiconductor die.

公开(公告)号：US20250131955A1

公开(公告)日：2025-04-24

申请号：US18756919

申请日：2024-06-27

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Wenlun Zhang

IPC: G11C11/4072 ,  G11C11/4078 ,  G11C11/4091

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for row hammer counter resets. Repeated access to an aggressor word line may cause increased data degradation in nearby victim word lines of the memory. The access count value of a given word line may be stored in counter memory cells positioned along that word line. The count values may be randomly or pseudo-randomly initialized. In some examples, a memory device may utilize residual charges that are present on the counter cells during start-up to initialize the counter memory cells. In some other examples, a memory device may utilize threshold voltage compensation (VtC) settings at start-up to initialize the counter memory cells. In some other examples, a memory device may utilize a combination of the residual charges that are present on the counter cells and VtC settings on start-up to initialize the counter memory cells.