公开(公告)号：US20100141139A1

公开(公告)日：2010-06-10

申请号：US12591426

申请日：2009-11-19

Applicant: Min-Suk Lee ,  Kwang-Jong Suh

Inventor： Min-Suk Lee ,  Kwang-Jong Suh

IPC: H01J17/49 ,  H01J9/20 ,  C09D1/00

CPC classification number: H01J11/40 ,  H01J9/02 ,  H01J11/12

Abstract: A protective layer for a PDP, includes a doping source layer containing at least one dopant, and a body layer which contacts the doping source layer and includes at least one dopant diffused from the doping source layer. The protective layer is capable of reducing dopant loss and avoiding trade-offs/conflicts between a donor dopant and an acceptor dopant.

Abstract translation: 用于PDP的保护层包括含有至少一种掺杂剂的掺杂源层和与掺杂源层接触并包括从掺杂源层扩散的至少一种掺杂物的体层。 保护层能够减少掺杂剂损失并避免施主掺杂剂和受主掺杂剂之间的权衡/冲突。

公开(公告)号：US07713639B2

公开(公告)日：2010-05-11

申请号：US11284621

申请日：2005-11-22

Applicant: Min-Suk Lee ,  Jong-Seo Choi ,  Suk-Ki Kim ,  Yuri Matulevich ,  Jae-Hyuk Kim ,  Soon-Sung Suh

Inventor： Min-Suk Lee ,  Jong-Seo Choi ,  Suk-Ki Kim ,  Yuri Matulevich ,  Jae-Hyuk Kim ,  Soon-Sung Suh

IPC: B32B9/00

CPC classification number: C03C17/3642 ,  C03C17/36 ,  C03C17/3657 ,  C03C17/3671 ,  C03C2217/40 ,  H01J11/12 ,  H01J11/40

Abstract: Provided are a protective layer made of magnesium oxide containing at least one rare earth element selected from the group consisting of the rare earth elements, in which the content of the at least one rare earth element is from about 5.0×10−5 to about 6.0×10−4 per 1 part by weight of the magnesium oxide, a composite for forming the protective layer, a method of forming the protective layer, and a plasma display panel including the protective layer. The protective layer can reduce a discharge delay time and the temperature dependency of the discharge delay time, and thus, is suitable for single scan and an increase in Xe content.

Abstract translation: 提供一种由氧化镁制成的保护层，其含有至少一种选自稀土元素的稀土元素，其中至少一种稀土元素的含量为约5.0×10 -5至约6.0 ×10-4 / 1重量份的氧化镁，用于形成保护层的复合体，形成保护层的方法和包括该保护层的等离子体显示面板。 保护层可以减少放电延迟时间和放电延迟时间的温度依赖性，因此适用于单次扫描和Xe含量的增加。

公开(公告)号：US07687341B2

公开(公告)日：2010-03-30

申请号：US12006142

申请日：2007-12-31

Applicant: Min-Suk Lee

Inventor： Min-Suk Lee

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8244

CPC classification number: H01L21/76897 ,  H01L27/10894

Abstract: A method for fabricating a semiconductor device includes forming at least one gate pattern over a substrate, forming a first insulation layer over the gate patterns and the substrate, etching the first insulation layer in a peripheral region to form at least one gate pattern spacer in the peripheral region, forming a second insulation layer over the substrate structure, etching the second insulation layer in a cell region to a given thickness, forming an insulation structure over the substrate structure, and etching the insulation structure, the etched first insulation layer and second insulation layer in the cell region to form a contact hole.

Abstract translation: 一种用于制造半导体器件的方法包括在衬底上形成至少一个栅极图案，在栅极图案和衬底之上形成第一绝缘层，在周边区域蚀刻第一绝缘层，以形成至少一个栅极图案间隔物 在衬底结构上形成第二绝缘层，将单元区域中的第二绝缘层蚀刻到给定厚度，在衬底结构上形成绝缘结构，以及蚀刻绝缘结构，蚀刻的第一绝缘层和第二绝缘层 层形成接触孔。

公开(公告)号：US20090153019A1

公开(公告)日：2009-06-18

申请号：US12314604

申请日：2008-12-12

Applicant: Min-Suk Lee ,  Jong-Seo Choi ,  Suk-Ki Kim ,  Yury Matulevich ,  Jae-Hyuk Kim ,  Soon-Sung Suh ,  Hee-Young Chu

Inventor： Min-Suk Lee ,  Jong-Seo Choi ,  Suk-Ki Kim ,  Yury Matulevich ,  Jae-Hyuk Kim ,  Soon-Sung Suh ,  Hee-Young Chu

IPC: H01J1/62 ,  B32B9/00 ,  B32B5/16 ,  B05D3/00

CPC classification number: H01J9/02 ,  H01J11/12 ,  H01J11/40 ,  Y10T428/258

Abstract: Provided are a protecting layer for a plasma display panel (PDP), a method of forming the same, and a PDP including the protecting layer. The protecting layer includes a magnesium oxide-containing layer having a surface to which magnesium oxide-containing particles having a magnesium vacancy-impurity center (VIC) are attached. The protecting layer is resistant to plasma ions and has excellent electron emission effects, and thus, a PDP including the protecting layer can be operated at low voltage with high discharge efficiency.

Abstract translation: 提供了一种用于等离子体显示面板（PDP）的保护层，其形成方法和包括该保护层的PDP。 保护层包括含有氧化镁的层，其具有附着有镁空位杂质中心（VIC）的含氧化镁的颗粒的表面。 保护层对等离子体离子具有抗性，具有优异的电子发射效果，因此能够以高放电效率在低电压下工作。

公开(公告)号：US20090047331A1

公开(公告)日：2009-02-19

申请号：US12093551

申请日：2006-10-27

Applicant: Sun Hee Kim ,  Sang Kil Lee ,  Min Suk Lee ,  Joon Pio Hong

Inventor： Sun Hee Kim ,  Sang Kil Lee ,  Min Suk Lee ,  Joon Pio Hong

IPC: A61K9/70 ,  A61L15/00 ,  A61P17/02

CPC classification number: A61L26/0066 ,  A61L15/28 ,  A61L26/0023 ,  A61L26/0095 ,  C08L5/08

Abstract: The present invention relates to a sustained release film formulation for healing wound comprising epidermal growth factor, chitosan, viscosity modifiers, plasticizers, and stabilizers. Specifically, the present invention relates to a sustained release film formulation for healing wound comprising epidermal growth factor as an effective ingredient and chitosan as a main base, and additionally comprising one or more antioxidants selected from the group consisting of EDTA and vitamin C; one or more viscosity modifiers selected from the group consisting of hydroxypropylmethylcellulose, gellan gum and pullulan; and one or more plasticizers selected from the group consisting of glycerin, propylene glycol, polyethylene glycol, polyvinyl alcohol and polyvinylpyrrolidone thereto. When the present film is attached to wound site, it absorbs exudation from wound site, and so is changed to hydrogel to keep wound site humid, which is good for wound-healing. And, the present film has superior attachment property to human body, and antifungal activity. Thus, the present film has more merits than simple ointment/cream formulation.

Abstract translation: 本发明涉及用于治疗伤口的持续释放膜制剂，其包括表皮生长因子，壳聚糖，粘度调节剂，增塑剂和稳定剂。 具体地，本发明涉及一种用于治疗伤口的持续释放膜制剂，其包含表皮生长因子作为有效成分和壳聚糖作为主要基质，并且还包含一种或多种选自EDTA和维生素C的抗氧化剂; 选自羟丙基甲基纤维素，结冷胶和支链淀粉的一种或多种粘度调节剂; 和一种或多种选自甘油，丙二醇，聚乙二醇，聚乙烯醇和聚乙烯吡咯烷酮的增塑剂。 当本膜附着于伤口部位时，吸收伤口部位的渗出物，因此变为水凝胶，保持伤口部位湿润，有利于伤口愈合。 而且，本发明的膜具有优异的人体附着性和抗真菌活性。 因此，本发明的薄膜比简单的软膏/霜剂具有更多的优点。

公开(公告)号：US20090004813A1

公开(公告)日：2009-01-01

申请号：US11951957

申请日：2007-12-06

Applicant: Min-Suk LEE

Inventor： Min-Suk LEE

IPC: H01L21/76

CPC classification number: H01L27/10823 ,  H01L27/10885 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method and system are provided for fabricating a semiconductor device that includes a vertical channel transistor. An area of a buried bit line is uniformly formed by an isolation trench. The width of the isolation trench is adjusted by controlling the thickness of spacers. Consequently, the area of the buried bit line is relatively large compared with that of a typical buried bit line. The resistance characteristics of the buried bit line are improved and stability and reliability of the semiconductor device are ensured.

Abstract translation: 提供了一种用于制造包括垂直沟道晶体管的半导体器件的方法和系统。 掩埋位线的区域由隔离沟槽均匀地形成。 通过控制间隔物的厚度来调节隔离沟槽的宽度。 因此，与典型的掩埋位线相比，埋入位线的面积相对较大。 提高了掩埋位线的电阻特性，确保了半导体器件的稳定性和可靠性。

公开(公告)号：US07405091B2

公开(公告)日：2008-07-29

申请号：US11020599

申请日：2004-12-21

Applicant: Sung-Kwon Lee ,  Tae-Woo Jung ,  Min-Suk Lee

Inventor： Sung-Kwon Lee ,  Tae-Woo Jung ,  Min-Suk Lee

IPC: G01R31/26 ,  H01L21/66

CPC classification number: H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention is a method for testing a contact open capable of effectively testing a contact open defect in an In-line as securing a mass productivity. The method includes the steps of: performing a photolithography process for forming a contact; forming a contact hole by performing a contact etching process after sampling at least one wafer; depositing a conductive layer on the wafer provided with the contact hole; isolating the conductive layer within the contact hole; performing a test for testing a contact open interface to check whether a remaining layer is existed in an interface between the conductive layer and a lower structure of the conductive layer; and performing a process for etching the contact of a main lot based on a test result.

Abstract translation: 本发明是一种用于测试接触开口的方法，其能够有效地测试在线的接触开口缺陷以确保批量生产率。 该方法包括以下步骤：执行用于形成接触的光刻工艺; 在对至少一个晶片取样之后进行接触蚀刻工艺形成接触孔; 在设置有接触孔的晶片上沉积导电层; 隔离接触孔内的导电层; 执行用于测试接触开放界面的测试以检查导电层和导电层的下部结构之间的界面中是否存在剩余层; 并且基于测试结果执行蚀刻主批次的接触的处理。

公开(公告)号：US07365000B2

公开(公告)日：2008-04-29

申请号：US10876783

申请日：2004-06-28

Applicant: Sung-Kwon Lee ,  Min-Suk Lee

Inventor： Sung-Kwon Lee ,  Min-Suk Lee

IPC: H01L21/4763 ,  H01L21/76

CPC classification number: H01L21/02063 ,  H01L21/02046 ,  H01L21/02052 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02222 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/31116 ,  H01L21/3125 ,  H01L21/316 ,  H01L21/31612 ,  H01L21/76837 ,  H01L21/76897 ,  H01L21/823475

Abstract: Disclosed is a method for fabricating a semiconductor device capable of preventing an inter-layer insulation layer from being damaged during a wet cleaning process due to a density difference created by reliance on a thickness of a SOG layer subjected to a curing process and of overcoming defects caused by an improper contact opening in a certain region and a punch taken place by micro voids of an APL layer. Particularly, the method includes the steps of: forming a plurality of conductive structure on a substrate; forming a spin-on-glass layer; curing the spin-on-glass layer; forming an advanced-planarization-layer on the spin-on-glass layer; and forming a plurality of contact holes by selectively etching the advanced-planarization-layer and the spin-on-glass layer, thereby exposing portions of the substrate.

Abstract translation: 公开了一种制造半导体器件的方法，该半导体器件能够防止层间绝缘层在湿式清洁过程中由于依赖于经历固化过程的SOG层的厚度和克服缺陷而产生的密度差而被损坏 这是由于某个区域的接触开口不正确以及由APL层的微小空隙发生的冲击造成的。 特别地，该方法包括以下步骤：在衬底上形成多个导电结构; 形成旋涂玻璃层; 固化旋涂玻璃层; 在旋涂玻璃层上形成先进的平面化层; 以及通过选择性地蚀刻高级平坦化层和旋涂玻璃层而形成多个接触孔，从而暴露基板的部分。

公开(公告)号：US20080081446A1

公开(公告)日：2008-04-03

申请号：US11904401

申请日：2007-09-27

Applicant: Sung-Kwon Lee ,  Min-Suk Lee

Inventor： Sung-Kwon Lee ,  Min-Suk Lee

IPC: H01L21/3205

CPC classification number: H01L21/76897 ,  H01L21/31116 ,  H01L21/31144

Abstract: A method for fabricating a semiconductor device includes forming a first pattern over a substrate, forming an oxide-based layer over the first pattern, forming a hard mask layer over the oxide-based layer, etching the hard mask layer at a first substrate temperature, and etching the oxide-based layer to form a second pattern, wherein the oxide-based layer is etched at a second substrate temperature which is greater than the first substrate temperature using a gas including fluorine (F) and carbon (C) as a main etch gas.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成第一图案，在第一图案上形成氧化物基层，在氧化物基层上形成硬掩模层，在第一衬底温度下蚀刻硬掩模层， 并且蚀刻所述氧化物基层以形成第二图案，其中所述氧化物基层在使用包含氟（F）和碳（C））为主要气体的第二基板温度下蚀刻，所述第二基板温度大于所述第一基板温度 蚀刻气体。

公开(公告)号：US20070173057A1

公开(公告)日：2007-07-26

申请号：US11567213

申请日：2006-12-06

Applicant: Min-Suk Lee ,  Jae-Young Lee

Inventor： Min-Suk Lee ,  Jae-Young Lee

IPC: H01L21/4763

CPC classification number: H01L21/76831 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76897

Abstract: A method for fabricating a storage node contact in a semiconductor device includes forming a plurality of bit line patterns, each bit line pattern including a bit line hard mask formed over a bit line conductive layer, forming an inter-layer insulation layer filled between the bit line patterns, planarizing the inter-layer insulation layer until top portions of the bit line hard masks are exposed, partially etching the inter-layer insulation layer to form first open regions, enlarging a width of the first open regions, forming a capping layer to cover the top portions of the bit line hard masks and to cover a surface of the first open regions, etching the capping layer and remaining portions of the inter-layer insulation layer between the bit line patterns to form second open regions below the first open regions, and forming storage node contacts filling in the first and second open regions.

Abstract translation: 一种用于在半导体器件中制造存储节点接触的方法包括形成多个位线图案，每个位线图案包括在位线导电层上形成的位线硬掩模，形成填充在位之间的层间绝缘层 使层间绝缘层平坦化，直到位线硬掩模的顶部露出为止，部分地蚀刻层间绝缘层以形成第一开放区域，扩大第一开放区域的宽度，形成覆盖层 覆盖位线硬掩模的顶部并且覆盖第一开放区域的表面，蚀刻覆盖层和层间绝缘层的剩余部分在位线图案之间以在第一开放区域下方形成第二开放区域 以及形成填充在第一和第二开放区域中的储存节点触点。