公开(公告)号：US06618290B1

公开(公告)日：2003-09-09

申请号：US09880366

申请日：2001-06-13

申请人： Janet S. Y. Wang ,  Narbeh Derhacobian

发明人： Janet S. Y. Wang ,  Narbeh Derhacobian

IPC分类号： G11C1604

CPC分类号： G11C16/0475

摘要： A method of programming that includes programming a fresh memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. Baking the programmed fresh cell causing a charge loss in the channel while the remaining charge within the channel is distributed more locally at the first region when compared to the distribution of charge prior to the baking.

摘要翻译： 一种编程方法，包括用包括第一区域和第二区域以及沟道上方的栅极的衬底编程新鲜存储器单元以及包含第一电荷量的电荷捕获区域。 烘烤编程的新鲜细胞，导致通道中的电荷损失，而与烘焙前的电荷分布相比，通道内的剩余电荷在第一区域更局部分布。

公开(公告)号：US06519182B1

公开(公告)日：2003-02-11

申请号：US09902332

申请日：2001-07-10

申请人： Narbeh Derhacobian ,  Daniel Sobek

发明人： Narbeh Derhacobian ,  Daniel Sobek

IPC分类号： G11C1604

CPC分类号： G11C16/3486 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3468

摘要： A programming operation using hot carrier injection is performed on a non volatile memory cell having an oxide-nitride-oxide structure by applying a first train of voltage pulses to he drain and a second train of voltage pulses to the gate. The programming method of the present invention prevents over-programming, minimizes programming time, and increases memory cell endurance and reliability.

摘要翻译： 对具有氧化物 - 氮化物 - 氧化物结构的非易失性存储单元进行使用热载流子注入的编程操作，通过向栅极施加第一列电压脉冲，将第二列电压脉冲施加到栅极。 本发明的编程方法防止过度编程，使编程时间最小化，并增加存储单元的耐久性和可靠性。

公开(公告)号：US06465303B1

公开(公告)日：2002-10-15

申请号：US09885490

申请日：2001-06-20

申请人： Mark T. Ramsbey ,  Narbeh Derhacobian ,  Janet Wang ,  Angela Hui ,  Tuan Pham ,  Ravi Sunkavalli ,  Mark Randolph

发明人： Mark T. Ramsbey ,  Narbeh Derhacobian ,  Janet Wang ,  Angela Hui ,  Tuan Pham ,  Ravi Sunkavalli ,  Mark Randolph

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： One aspect of the present invention relates to a method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, involving the steps of providing a semiconductor substrate having a core region and periphery region, the core region containing SONOS type memory cells and the periphery region containing gate transistors; implanting a first implant into the core region and a first implant into the periphery region of the semiconductor substrate; forming a spacer material over the semiconductor substrate; masking the core region and forming spacers adjacent the gate transistors in the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.

摘要翻译： 本发明的一个方面涉及一种在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性半导体存储器件中形成间隔物的方法，包括以下步骤：提供具有核心区域和外围区域的半导体衬底， 包含SONOS型存储单元的核心区域和包含栅极晶体管的外围区域; 将第一注入植入到所述芯区域中，并将第一注入植入所述半导体衬底的周边区域; 在所述半导体衬底上形成隔离材料; 掩蔽所述芯区域并在所述周边区域中形成与所述栅极晶体管相邻的间隔物; 以及将第二植入物植入所述半导体衬底的周边区域。

公开(公告)号：US06456536B1

公开(公告)日：2002-09-24

申请号：US09884409

申请日：2001-06-19

申请人： Daniel Sobek ,  Timothy J. Thurgate ,  Janet Wang ,  Narbeh Derhacobian

发明人： Daniel Sobek ,  Timothy J. Thurgate ,  Janet Wang ,  Narbeh Derhacobian

IPC分类号： G11C1604

CPC分类号： G11C16/0475 ,  G11C11/5671 ,  G11C16/12

摘要： A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a constant first voltage across the gate, applying a second constant voltage across the first region and applying a third voltage that is constant and negative to the substrate so that the effect of spillover electrons is substantially reduced when compared with when the third constant voltage is absent.

摘要翻译： 一种用衬底编程存储单元的方法，该衬底包括第一区域和具有通道的第二区域和沟道上方的栅极以及包含第一电荷量的电荷捕获区域。 该方法包括在栅极上施加恒定的第一电压，在第一区域上施加第二恒定电压，并向衬底施加恒定和负的第三电压，使得当与第三区域相比时，溢出电子的效应显着降低 不存在恒定电压。

公开(公告)号：US06456533B1

公开(公告)日：2002-09-24

申请号：US09796282

申请日：2001-02-28

申请人： Darlene G. Hamilton ,  Narbeh Derhacobian ,  Janet S.Y. Wang ,  Kulachet K.T. Tanpairoj

发明人： Darlene G. Hamilton ,  Narbeh Derhacobian ,  Janet S.Y. Wang ,  Kulachet K.T. Tanpairoj

IPC分类号： G11C1134

CPC分类号： G11C16/3409 ,  G11C11/5671 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/50 ,  G11C29/50004

摘要： A method and system for programming of the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. Furthermore, by utilizing substantially high gate and drain voltages during programming, programming times are kept short without degrading charge loss. A methodology is provided that determines the charge loss for single bit operation during program and erase cycles. The charge losses over cycling and stress are then utilized to determine an appropriate delta VT to be programmed into a command logic and state machine.

摘要翻译： 用于编程双位存储器单元的存储器阵列的正常位的方法和系统通过以基本上高的delta VT编程来实现。 基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在更高的温度应力和/或客户操作之后一致地擦除数据。 此外，通过在编程期间利用基本上高的栅极和漏极电压，编程时间保持较短，而不会降低电荷损失。 提供了一种确定在编程和擦除周期期间单位操作的电荷损失的方法。 然后利用循环和应力的电荷损耗来确定要编程到命令逻辑和状态机中的适当的增量VT。

公开(公告)号：US06442074B1

公开(公告)日：2002-08-27

申请号：US09795854

申请日：2001-02-28

申请人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian

发明人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445 ,  G11C29/50

摘要： A method and system for programming and erasing the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT and an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. After the first erase pulse, the erase verify routine is performed on all the IO's together. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. This erase pulse that provides a substantially high electric field is selected to erase band to band currents for the entire array that are larger than can be supplied by drain pumps.

摘要翻译： 用于编程和擦除双位存储器单元的存储器阵列的正常位的方法和系统通过以基本上高的delta VT和擦除脉冲进行编程来实现，该擦除脉冲为扇区1中的每个I / O提供基本上高的电场 一次 在第一个擦除脉冲之后，擦除验证程序在所有IO上一起执行。 基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在较高的温度应力和/或客户操作之后一致地擦除数据。 选择提供基本上高的电场的擦除脉冲，以消除整个阵列的频带电流，其大于由排水泵提供的频带电流。

公开(公告)号：US06331953B1

公开(公告)日：2001-12-18

申请号：US09697813

申请日：2000-10-26

申请人： Janet S. Y. Wang ,  Narbeh Derhacobian ,  Daniel Sobek

发明人： Janet S. Y. Wang ,  Narbeh Derhacobian ,  Daniel Sobek

IPC分类号： G11C700

CPC分类号： G11C16/344 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/14 ,  G11C16/3445 ,  H01L29/7923

摘要： A method of erasing a memory cell that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes: applying a voltage across the gate and the first region in accordance with a coarse erase sequence of voltages so that a portion of the first amount of charge is removed from the charge trapping region; and applying a voltage across the gate and the first region in accordance with a fine erase sequence of voltages so that a portion of the first amount of charge is removed from the charge trapping region.

摘要翻译： 一种擦除存储单元的方法，该存储单元包括第一区域和第二区域以及通道之间的通道，以及包含第一电荷量的电荷捕获区域。 该方法包括：根据粗略擦除电压序列施加跨栅极和第一区域的电压，使得第一电荷量的一部分从电荷捕获区域去除; 以及根据电压的精细擦除序列施加跨越栅极和第一区域的电压，使得第一电荷量的一部分从电荷捕获区域去除。

公开(公告)号：US06327183B1

公开(公告)日：2001-12-04

申请号：US09480868

申请日：2000-01-10

申请人： Joseph G. Pawletko ,  K. Michael Han ,  Narbeh Derhacobian

发明人： Joseph G. Pawletko ,  K. Michael Han ,  Narbeh Derhacobian

IPC分类号： G11C700

CPC分类号： G11C5/147 ,  G11C16/12 ,  G11C16/3468

摘要： A voltage control circuit that narrows the distribution of threshold voltages of memory cells by using nonlinearly incremented programming voltages. To do so, the voltage control circuit applies to the memory cells a first program pulse of a first voltage, a second program pulse of a second voltage to the memory cell, and a third program pulse of a third voltage, where the difference between the third voltage and the second voltage is less than the difference between the second voltage and the first voltage.

摘要翻译： 一种电压控制电路，其通过使用非线性递增的编程电压来缩小存储器单元的阈值电压的分布。 为此，电压控制电路向存储器单元施加第一电压的第一编程脉冲，到存储单元的第二电压的第二编程脉冲和第三电压的第三编程脉冲， 第三电压，第二电压小于第二电压和第一电压之间的差。

公开(公告)号：US06188606B1

公开(公告)日：2001-02-13

申请号：US09369600

申请日：1999-08-06

申请人： Narbeh Derhacobian ,  Hao Fang ,  Michael Han

发明人： Narbeh Derhacobian ,  Hao Fang ,  Michael Han

IPC分类号： G11C1604

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5642

摘要： A method and circuit for sensing multi states of a NAND memory cell by varying source bias, at a constant gate voltage, preferably zero volts, generating a memory cell current in response to the source bias, and sensing the memory cell state.

摘要翻译： 一种用于通过在恒定栅极电压（优选为零伏特）下改变源偏置来感测NAND存储器单元的多状态的方法和电路，响应于源极偏置产生存储单元电流，并感测存储单元状态。

公开(公告)号：US6143612A

公开(公告)日：2000-11-07

申请号：US172090

申请日：1998-10-14

申请人： Narbeh Derhacobian ,  Pau-ling Chen ,  Hao Fang ,  Timothy Thurgate

发明人： Narbeh Derhacobian ,  Pau-ling Chen ,  Hao Fang ,  Timothy Thurgate

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/66575 ,  H01L21/76216 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/78

摘要： A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is forced while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, and employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants. Appropriate openings are formed in the field implant blocking mask so that the field implant occurs at the edges of the junctions, thus achieving low leakage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

摘要翻译： 强制显示高门控二极管击穿电压，低泄漏和低体效应的高电压晶体管，同时避免过多数量的昂贵的掩蔽步骤。 实施例包括通过掩蔽来自常规场注入的高电压结点来提供高门控二极管击穿电压，从传统的阈值调整注入屏蔽源极/漏极区域，以及采用非常轻掺杂的n型注入来代替常规的n +和 LDD植入物。 在场注入阻挡掩模中形成适当的开口，使得场注入发生在接合部的边缘处，从而实现低泄漏。 场注入阻挡掩模在沟道区域上延伸，从而产生具有低体效应的晶体管。