公开(公告)号：US20090280653A1

公开(公告)日：2009-11-12

申请号：US12505414

申请日：2009-07-17

Applicant: TING CHEONG ANG

Inventor： TING CHEONG ANG

IPC: H01L21/31

CPC classification number: H01L21/02131 ,  C23C16/30 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31604 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/7684 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric layer is formed by a CVD process. Furthermore, the method includes forming a diffusion barrier layer overlying the dielectric layer. In addition, the method includes forming a conductive layer overlying the diffusion barrier layer. Additionally, the method includes reducing the thickness of the conductive layer using a chemical-mechanical polishing process. The CVD process utilizes fluorine as a reactant to form the dielectric layer. In addition, the dielectric layer is associated with a dielectric constant equal or less than 3.3.

Abstract translation: 提供一种形成半导体器件的方法。 在一个实施例中，该方法包括提供具有表面区域的半导体衬底。 表面区域包括覆盖半导体衬底的一个或多个层。 此外，该方法包括沉积覆盖表面区域的介电层。 介电层通过CVD工艺形成。 此外，该方法包括形成覆盖在电介质层上的扩散阻挡层。 此外，该方法包括形成覆盖扩散阻挡层的导电层。 另外，该方法包括使用化学机械抛光工艺来减小导电层的厚度。 CVD工艺利用氟作为反应物形成电介质层。 此外，介电层与等于或小于3.3的介电常数相关联。

公开(公告)号：US06833606B2

公开(公告)日：2004-12-21

申请号：US10289684

申请日：2002-11-07

Applicant: Hiroshi Nakamura ,  Ting Cheong Ang ,  Kian Siong Ang ,  Subrata Halder ,  Geok Ing Ng

Inventor： Hiroshi Nakamura ,  Ting Cheong Ang ,  Kian Siong Ang ,  Subrata Halder ,  Geok Ing Ng

IPC: H01L2706

CPC classification number: H01L27/0605 ,  H01L21/8252

Abstract: In the present invention, a semiconductor device is formed which includes an MIM capacitor located on the upper surface of a heterostructure from which the emitter, base and collector sections of a nearby HBT are defined. In this way the capacitor and HBT share a substantially common structure, with the base and emitter electrodes of the HBT fashioned from the same metal layers as the upper and lower capacitor plates, respectively. Furthermore, as the insulator region of the capacitor is formed prior to definition of the HBT structure, the dielectric material used can be deposited by means of a plasma enhanced process, without damaging the HBT structure.

Abstract translation: 在本发明中，形成半导体器件，其包括位于异质结构的上表面上的MIM电容器，从其定义附近HBT的发射极，基极和集电极部分。 以这种方式，电容器和HBT分别具有基本上共同的结构，HBT的基极和发射极电极分别由与上部和下部电容器板相同的金属层制成。 此外，由于在定义HBT结构之前形成电容器的绝缘体区域，所以使用的电介质材料可以通过等离子体增强工艺沉积，而不会损坏HBT结构。

公开(公告)号：US06492242B1

公开(公告)日：2002-12-10

申请号：US09609447

申请日：2000-07-03

Applicant: Alex See ,  Cher Liang Randall Cha ,  Shyuz Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

Inventor： Alex See ,  Cher Liang Randall Cha ,  Shyuz Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

IPC: H01L2120

CPC classification number: H01L28/40 ,  H01L21/31683

Abstract: A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures. A second iteration features the exposure of specific regions of an underlying metal layer, to a UV, or to an I line exposure procedure, performed in an oxidizing ambient, with the regions of an underlying metal layer exposed to the UV or I line procedure, via clear regions in an overlying photolithographic plate. This procedure also results in the formation of a high K layer, on a top portion of the underlying metal layer.

Abstract translation: 在高于周围结构所经历的温度的温度下进行的金属氧化物 - 金属电容器结构的高介电常数（高K）层，其特征在于底层金属层的局部氧化， 已经开发 该方法的第一次迭代的特征在于在氧化环境中使用对底层金属层的局部区域进行的激光烧蚀程序。 激光烧蚀过程仅在激光点产生所需的高温，允许在该温度下产生高K层，而不直接暴露于激光烧蚀过程的半导体衬底上的周围结构保持在较低温度 。 第二次迭代的特征在于在氧化环境中进行的底层金属层的特定区域到UV或I线曝光程序，暴露于UV或I线程序的下面的金属层的区域， 通过覆盖光刻板中的透明区域。 该过程还导致在下面的金属层的顶部上形成高K层。

公开(公告)号：US06275089B1

公开(公告)日：2001-08-14

申请号：US09482048

申请日：2000-01-13

Applicant: Jun Song ,  Ting Cheong Ang ,  Shyue Fong Quek ,  Lap Chan

Inventor： Jun Song ,  Ting Cheong Ang ,  Shyue Fong Quek ,  Lap Chan

IPC: H03K508

CPC classification number: H01L27/0251

Abstract: A transient protection circuit is described which provides electrostatic discharge (ESD) protection for an internal circuit of an IC. The transient protection circuit comprises two Zener diodes connected in series between the input pad and the internal circuit of the IC. A sufficiently large ESD pulse will drive one the two Zener diodes into breakdown mode, thereby reducing the magnitude of the ESD pulse to the remainder of the circuit. Resistive means are paralleled with the Zener diodes to provide a signal path at non-ESD voltages. To help shunt the ESD current away from the internal circuit, PMOS and NMOS transistors are connected in parallel between the positive and the negative voltage supply and their junction is connected to the internal circuit. Negative ESD pulses cause the PMOS transistors to turn on, dumping the ESD energy into the positive voltage supply, while positive ESD pulses cause the NMOS transistors to turn on, dumping the ESD energy into the negative voltage supply. Voltage changes, caused by currents flowing through the resistive means, trigger parasitic SCRs into conduction to provide the bulk of the ESD protection.

Abstract translation: 描述了为IC的内部电路提供静电放电（ESD）保护的瞬态保护电路。 瞬态保护电路包括串联连接在输入焊盘和IC内部电路之间的两个齐纳二极管。 足够大的ESD脉冲将驱动两个齐纳二极管中的一个进入击穿模式，从而将ESD脉冲的幅度减小到电路的其余部分。 电阻性装置与齐纳二极管并联，以在非ESD电压下提供信号路径。 为了有助于将ESD电流从内部电路分流，PMOS和NMOS晶体管并联连接在正电压和负电源之间，它们的结连接到内部电路。 负ESD脉冲导致PMOS晶体管导通，将ESD能量转储到正电压源中，而正的ESD脉冲使NMOS晶体管导通，将ESD能量转储到负电源。 由电流流过电阻的电流引起的电压变化会将寄生的SCR触发导通，以提供大量的ESD保护。

公开(公告)号：US06258677B1

公开(公告)日：2001-07-10

申请号：US09409875

申请日：1999-10-01

Applicant: Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

Inventor： Ting Cheong Ang ,  Shyue Fong Quek ,  Sang Yee Loong ,  Jun Song

IPC: H01L21336

CPC classification number: H01L29/0847 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/76283 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66651

Abstract: A method of fabricating a transistor, comprising the following steps. A silicon semiconductor structure having spaced, raised, wedge-shaped dielectric isolation regions defining an active region there between is provided. Epitaxial silicon is grown over the active area to form an SEG region. A dummy gate is formed over the SEG region. Raised epitaxial silicon layers are grown over the SEG region adjacent the dummy gate. The dummy gate is removed, exposing the interior side walls of the raised epitaxial silicon layers. Sidewall spacers are formed on the exposed sidewalls of the raised epitaxial silicon layers. A gate oxide layer is grown over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. A layer of polysilicon is deposited over the structure and is planarized to form a gate conductor over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. The sidewall spacers are removed. No HDP process trench fill is required to form the STIs and no CMP process is required to planarized the STIs.

Abstract translation: 一种制造晶体管的方法，包括以下步骤。 提供了具有限定其间的有源区域的具有间隔开的凸起的楔形介电隔离区域的硅半导体结构。 在活性区域上生长外延硅以形成SEG区域。 在SEG区域上形成一个虚拟门。 凸起的外延硅层生长在与虚拟栅极相邻的SEG区域上。 去除虚拟栅极，暴露凸起的外延硅层的内侧壁。 在凸起的外延硅层的暴露的侧壁上形成侧壁间隔物。 栅极氧化物层生长在SEG区域上并且在凸起的外延硅层的侧壁间隔物之间​​。 在该结构上沉积一层多晶硅，并将其平坦化，以在SEG区域和凸出的外延硅层的侧壁间隔物之间​​形成栅极导体。 去除侧壁间隔物。 不需要HDP工艺沟槽填充来形成STI，并且不需要CMP工艺来平坦化STI。

公开(公告)号：US06248618B1

公开(公告)日：2001-06-19

申请号：US09415246

申请日：1999-10-12

Applicant: Shyue Fong Quek ,  Ting Cheong Ang ,  Puay Ing Ong ,  Sang Yee Loong

Inventor： Shyue Fong Quek ,  Ting Cheong Ang ,  Puay Ing Ong ,  Sang Yee Loong

IPC: H01L218238

CPC classification number: H01L21/823857 ,  Y10S438/981

Abstract: A method of forming thick and thin gate oxides comprising the following steps. A silicon semiconductor substrate having first and second active areas separated by shallow isolation trench regions is provided. Oxide growth is selectively formed over the first active area by UV oxidation to form a first gate oxide layer having a first predetermined thickness. The first and second active areas are then simultaneously oxidized whereby the first predetermined thickness of the first gate oxide layer is increased to a second predetermined thickness and a second gate oxide layer having a predetermined thickness is formed in the second active area. The second predetermined thickness of the first oxide layer in the first active area is greater than the predetermined thickness of the second oxide layer in the second active area.

Abstract translation: 一种形成厚薄的栅极氧化物的方法，包括以下步骤。 提供具有由浅隔离沟槽区域隔开的第一和第二有源区的硅半导体衬底。 通过UV氧化在第一有源区上选择性地形成氧化物生长，以形成具有第一预定厚度的第一栅氧化层。 然后，第一和第二有源区域被同时氧化，由此第一栅极氧化物层的第一预定厚度增加到第二预定厚度，并且在第二有源区域中形成具有预定厚度的第二栅极氧化物层。 第一有源区中的第一氧化物层的第二预定厚度大于第二有源区中第二氧化物层的预定厚度。