公开(公告)号：US5341326A

公开(公告)日：1994-08-23

申请号：US833045

申请日：1992-02-10

申请人： Satoru Takase ,  Natsuki Kushiyama ,  Tohru Furuyama

发明人： Satoru Takase ,  Natsuki Kushiyama ,  Tohru Furuyama

IPC分类号： G11C11/405 ,  G11C11/56 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/24 ,  G11C11/34

CPC分类号： G11C11/565

摘要： A semiconductor memory cell comprises a cascade gate including a plurality of cascade-connected MOS transistors and having one end connected to a first node, and a plurality of capacitors for data storage connected at one end to the MOS transistors, respectively at the end remote from the node, and there is a predetermined regulation in relation of the capacitance of the capacitors.

摘要翻译： 半导体存储单元包括级联栅极，其包括多个级联连接的MOS晶体管，并且其一端连接到第一节点;以及多个用于数据存储的电容器，其一端连接到MOS晶体管，分别在远离 节点，并且存在关于电容器的电容的预定调节。

公开(公告)号：US5317540A

公开(公告)日：1994-05-31

申请号：US850318

申请日：1992-03-12

申请人： Tohru Furuyama

发明人： Tohru Furuyama

IPC分类号： G11C8/04 ,  G11C11/56 ,  G11C13/00

CPC分类号： G11C8/04 ,  G11C11/565 ,  G11C19/00

摘要： A semiconductor memory device comprises a memory cell array in which cascade-gate dynamic memory cells are arranged in a matrix and which contains word lines connected in common to the memory cells in the same row and bit lines connected in common to the memory cells in the same column, and serial access control means which serially accesses a plurality of memory cells in a given column of the memory cell array, reads a plurality of bits of information in time-sequence from one of the memory cells storing information, and then sequentially rewrites the bits of information into a different memory cell unused for storing valid data, in the same column where the memory cell exists.

摘要翻译： 半导体存储器件包括存储单元阵列，其中级联栅极动态存储器单元被布置在矩阵中，并且其包含与公共连接到存储器单元中的字线相同的行和位线，公共连接到存储单元中的存储器单元 同一列和串行访问控制装置，其串行访问存储单元阵列的给定列中的多个存储单元，从存储信息的存储单元之一读取时间序列中的多个位信息，然后顺序地重写 在存储单元存在的同一列中，信息的比特位于不存储有效数据的不同存储单元中。

公开(公告)号：US5298433A

公开(公告)日：1994-03-29

申请号：US813511

申请日：1991-12-26

申请人： Tohru Furuyama

发明人： Tohru Furuyama

IPC分类号： H01L21/66 ,  G01R31/28 ,  G01R31/30 ,  G06F11/20 ,  G11C11/401 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/08 ,  G11C7/00

CPC分类号： G01R31/30 ,  G01R31/2831 ,  G01R31/2884 ,  G01R31/2856 ,  Y10S148/162

摘要： A method for manufacturing semiconductor devices according to this invention, comprises the wafer manufacturing step of forming an integrated circuit with a redundant circuit in each of a plurality of chip areas on a semiconductor wafer and also forming at least one stress testing terminal that applies a stress testing voltage or stress testing signal to the interconnections other than those for power supply in the integrated circuit for each of the chip areas or for every certain number of the chip areas, the step of, after the wafer manufacturing step, screening failures by applying a specified stress testing control signal or stress voltage to a certain number of chip areas with the stress testing terminal in contact with a contact terminal of a tester in the wafer state, the step of, after the screening step, judging whether or not the electrical characteristics of each chip area are acceptable through die sort test, the step of remedying an integrated circuit in a chip area judged to be defective in the judging step, by means of the redundant circuit, and the assembly step of, after the remedying step, separating the chip areas into individual elements and then assembling them into an integrated circuit device.

摘要翻译： 根据本发明的制造半导体器件的方法包括在半导体晶片上的多个芯片区域中的每一个中形成具有冗余电路的集成电路的晶片制造步骤，还形成至少一个施加应力的应力测试端子 测试电压或压力测试信号到除芯片区域之间的集成电路中的电源以外的互连或针对每一定数量的芯片区域的互连，晶片制造步骤之后的步骤是通过应用 指定的应力测试控制信号或应力电压到一定数量的芯片区域，其中应力测试端子与晶片状态下的测试仪的接触端接触，步骤之后，筛选步骤后，判断电特性 的每个芯片面积都可以通过芯片分类测试来接受，在芯片区域中对集成电路进行补救的步骤进行判断 在判断步骤中通过冗余电路存在缺陷，并且在补救步骤之后的组装步骤将芯片区域分离成单个元件，然后将它们组装成集成电路器件。

公开(公告)号：US5258954A

公开(公告)日：1993-11-02

申请号：US908744

申请日：1992-07-06

申请人： Tohru Furuyama

发明人： Tohru Furuyama

IPC分类号： G11C29/08 ,  G11C29/34 ,  G11C29/50 ,  G11C29/00 ,  G11C8/00

CPC分类号： G11C29/34 ,  G11C29/50 ,  G11C11/401 ,  G11C11/41 ,  G11C29/08

摘要： A semiconductor memory includes circuitry for driving plural word lines in a test mode. The semiconductor memory includes a plurality of memory cells; a plurality of word lines connected to the memory cells; a plurality of bit lines connected to the memory cells; and a drive circuit connected to the word lines for, in a test mode, selectively driving all the word lines or, alternatively, driving a select number of word lines.

摘要翻译： 半导体存储器包括用于在测试模式下驱动多个字线的电路。 半导体存储器包括多个存储单元; 连接到所述存储单元的多个字线; 连接到存储器单元的多个位线; 以及连接到字线的驱动电路，用于在测试模式下选择性地驱动所有字线，或者替代地驱动选定数量的字线。