公开(公告)号：US08422295B1

公开(公告)日：2013-04-16

申请号：US13332402

申请日：2011-12-21

Applicant: Chih-He Lin ,  Wen-Pin Lin ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

Inventor： Chih-He Lin ,  Wen-Pin Lin ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

IPC: G11C14/00

CPC classification number: G11C14/009

Abstract: A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage. A second terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element are coupled to a first terminal of the latch unit. A second terminal of the third non-volatile memory element and a first terminal of the fourth non-volatile memory element are coupled to a second terminal of the latch unit. Second terminals of the second and the fourth non-volatile memory element are coupled to a first terminal of the switch. A second terminal of the switch is coupled to a third voltage.

Abstract translation: 提供了非易失性随机存取存储器（NV-RAM）及其操作方法。 NV-RAM包括锁存单元，开关和第一至第四非易失性存储元件。 第一和第三非易失性存储元件的第一端分别耦合到第一电压和第二电压。 第一非易失性存储元件的第二端子和第二非易失性存储器元件的第一端子耦合到锁存单元的第一端子。 第三非易失性存储元件的第二端子和第四非易失性存储元件的第一端子耦合到锁存单元的第二端子。 第二和第四非易失性存储元件的第二端子耦合到开关的第一端子。 开关的第二端子耦合到第三电压。

公开(公告)号：US20120018723A1

公开(公告)日：2012-01-26

申请号：US12967932

申请日：2010-12-14

Applicant: Keng-Li SU ,  Chih-Sheng Lin ,  Wen-Pin Lin ,  John H. Lau

Inventor： Keng-Li SU ,  Chih-Sheng Lin ,  Wen-Pin Lin ,  John H. Lau

IPC: H01L23/58 ,  H01L21/66

CPC classification number: H01L22/34

Abstract: A test structure including at least one ground pad, an input pad, at least one first through-silicon via (TSV), at least one second TSV and an output pad is disclosed. The ground pad receives a ground signal during a test mode. The input pad receives a test signal during the test mode. The first TSV is coupled to the input pad. The output pad is coupled to the second TSV. No connection line occurs between the first and the second TSVs. During the test mode, a test result is obtained according to the signal of at least one of the first and the second TSVs, and structural characteristics can be obtained according to the test result.

Abstract translation: 公开了包括至少一个接地焊盘，输入焊盘，至少一个第一穿透硅通孔（TSV），至少一个第二TSV和输出焊盘的测试结构。 接地焊盘在测试模式下接收接地信号。 在测试模式期间，输入焊盘接收测试信号。 第一TSV耦合到输入板。 输出焊盘耦合到第二TSV。 在第一和第二TSV之间不发生连接线。 在测试模式期间，根据第一和第二TSV中的至少一个的信号获得测试结果，并且可以根据测试结果获得结构特征。

公开(公告)号：US20110317483A1

公开(公告)日：2011-12-29

申请号：US13215491

申请日：2011-08-23

Applicant: Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

Inventor： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

IPC: G11C11/00

CPC classification number: G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092

Abstract: A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.

Abstract translation: 提供了一种用于将写入数据存储到存储单元中的数据编程电路。 数据编程电路包括控制电路和电流产生电路。 控制电路根据写入数据生成控制信号。 电流产生电路向存储单元提供写入电流以改变存储单元的结晶状态。 写入电流具有对应于写入数据的脉冲宽度，并且结晶状态对应于写入数据。

公开(公告)号：US20110270555A1

公开(公告)日：2011-11-03

申请号：US12851547

申请日：2010-08-05

Applicant: Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

Inventor： Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

IPC: G06F19/00 ,  G01R19/00

CPC classification number: G01R31/2837 ,  G11C13/00 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409 ,  H01L22/34

Abstract: A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result. The compensation signal generator is connected to the process variation detector, and produces a corresponding compensation signal according to the current comparison result.

Abstract translation: 提供了一种过程变化检测装置和工艺变化检测方法。 过程变化检测装置包括处理变化检测器和补偿信号发生器。 过程变化检测器包括第一过程变化检测部件，第二过程变化检测部件和电流比较器。 第一处理变化检测部件的通道是第一导电型，第二处理变化检测部件的通道是第二导电型，其中上述第一导电类型与第二导电类型不同。 电流比较器连接到第一处理变化检测部件和第二处理变化检测部件，用于比较两个部件之间的电流差异并输出当前的比较结果。 补偿信号发生器连接到过程变化检测器，并根据当前比较结果产生相应的补偿信号。

公开(公告)号：US08014194B2

公开(公告)日：2011-09-06

申请号：US12561245

申请日：2009-09-16

Applicant: Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

Inventor： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0004

Abstract: A phase change memory (PCM) in which the phase change storage element is crystallized by a gradually increasing/decreasing operating current. The PCM comprises a switching circuit, the phase change storage element, a bit select switch, a pulse generating module, and a counting module. The switching circuit comprises a plurality of switches, selectively providing branch paths to an output terminal of a current source. The bit select switch controls the conduction between the phase change storage element and the output terminal of the current source. The pulse generating module outputs a pulse signal oscillating between high and low voltage levels. When enabled, the counting module counts the oscillations of the pulse signal, and outputs the count result by a set of digital data. The set of digital data are coupled to the switching circuit to control the switches therein.

Abstract translation: 相变存储元件通过逐渐增加/减小的工作电流而结晶化的相变存储器（PCM）。 PCM包括开关电路，相变存储元件，位选择开关，脉冲发生模块和计数模块。 开关电路包括多个开关，选择性地提供到电流源的输出端的分支路径。 位选择开关控制相变存储元件与电流源的输出端之间的导通。 脉冲发生模块输出在高电平和低电压电平之间振荡的脉冲信号。 当使能时，计数模块对脉冲信号的振荡进行计数，并通过一组数字数据输出计数结果。 该组数字数据耦合到开关电路以控制其中的开关。

公开(公告)号：US07889547B2

公开(公告)日：2011-02-15

申请号：US12344709

申请日：2008-12-29

Applicant: Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

Inventor： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C5/147 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0064 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2013/0066 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2029/5006

Abstract: A memory having a memory cell, a resistance estimator and a write current generator. The resistance estimator is coupled to the memory cell to estimate the resistance of the memory cell and outputs an estimated resistance level. According to the estimated resistance level, the write current generator generates a write current to flow through the memory cell and to change the resistance of the memory cell. The write current is in a pulse form, and the write current generator sets the pulse width, or magnitude, or both the pulse width and the magnitude of the write current according to the estimated resistance level.

Abstract translation: 具有存储单元的存储器，电阻估计器和写入电流发生器。 电阻估计器耦合到存储器单元以估计存储器单元的电阻并输出估计的电阻电平。 根据估计的电阻电平，写入电流发生器产生写入电流流过存储器单元并改变存储单元的电阻。 写入电流是脉冲形式，并且写入电流发生器根据估计的电阻电平设置脉冲宽度或幅度或脉冲宽度和写入电流的幅度。

公开(公告)号：US07773410B2

公开(公告)日：2010-08-10

申请号：US12165761

申请日：2008-07-01

Applicant: Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

Inventor： Shyh-Shyuan Sheu ,  Lieh-Chiu Lin ,  Pei-Chia Chiang ,  Wen-Pin Lin

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0064

Abstract: An embodiment of a writing system for a phase change memory based on a present application is disclosed. The writing system comprises a first phase change memory (PCM) cell, a second PCM cell, a first writing circuit and a verifying circuit. The first writing circuit executes a writing procedure, receives and writes a first data to the first PCM cell. The verifying circuit executes a verifying procedure and the circuit further comprises a processing unit and a second writing circuit. The processing unit reads and compares the data stored in the second PCM cell with a second data. The second writing circuit writes the second data to the second PCM cell when the data stored in the second PCM cell and the second data are not matched.

Abstract translation: 公开了一种基于本申请的相变存储器的写入系统的实施例。 该写入系统包括第一相变存储器（PCM）单元，第二PCM单元，第一写入电路和验证电路。 第一写入电路执行写入过程，将第一数据接收并写入第一PCM单元。 验证电路执行验证过程，并且电路还包括处理单元和第二写入电路。 处理单元读取并比较存储在第二PCM单元中的数据与第二数据。 当存储在第二PCM单元中的数据和第二数据不匹配时，第二写入电路将第二数据写入第二PCM单元。

公开(公告)号：US20100165723A1

公开(公告)日：2010-07-01

申请号：US12563971

申请日：2009-09-21

Applicant: Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

Inventor： Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0092

Abstract: A phase change memory with an operating current that can be gradually increased or gradually decreased. The phase change memory has a phase change storage element, a transistor, and a control circuit. The transistor is operable to adjust the operating current flowing through the phase change storage element. The transistor has a first terminal coupled to a voltage source, a second terminal coupled to the phase change storage element, and a control terminal receiving a control signal from the control circuit. The control circuit is specially designed to limit the transistor in a linear region.

Abstract translation: 具有可逐渐增加或逐渐减小的工作电流的相变存储器。 相变存储器具有相变存储元件，晶体管和控制电路。 晶体管可操作以调节流过相变存储元件的工作电流。 晶体管具有耦合到电压源的第一端子，耦合到相变存储元件的第二端子以及从控制电路接收控制信号的控制端子。 控制电路专门设计用于将晶体管限制在线性区域。

公开(公告)号：US07627973B2

公开(公告)日：2009-12-08

申请号：US11879823

申请日：2007-07-18

Applicant: Wen-Pin Lin ,  Kuan-Cheng Hsieh ,  Wen-Hung Huang

Inventor： Wen-Pin Lin ,  Kuan-Cheng Hsieh ,  Wen-Hung Huang

IPC: A47G1/06

CPC classification number: G06F1/1601 ,  Y10T24/309 ,  Y10T24/344

Abstract: A frame structure disposing thereon a specific one of plural display panels having at least a first thickness and a second thickness is provided. The frame structure includes a receptacle disposing thereon the specific display panel having a specific thickness equivalent to one of the first and second thicknesses, a set of first fastening elements, each of which includes a first protrusion, and a set of second fastening elements, each of which includes a second protrusions, wherein the sets of first fastening elements and second fastening elements are peripherally disposed around the receptacle, each of the first protrusions has a height corresponding to the first thickness and each of the second protrusions has a height corresponding to the second thickness, whereby the specific display panel is fastened by one of sets of the first and second protrusions having the respective height corresponding to the specific thickness.

Abstract translation: 设置有具有至少第一厚度和第二厚度的多个显示面板中的特定一个的框架结构。 框架结构包括在其上设置具有与第一和第二厚度之一相当的特定厚度的特定显示面板的容器，一组第一紧固元件，每个第一紧固元件包括第一突起和一组第二紧固元件，每个 其中包括第二突起，其中第一紧固元件和第二紧固元件组围绕插座周边设置，每个第一突起具有对应于第一厚度的高度，并且每个第二突起的高度对应于 第二厚度，由此特定显示面板通过具有对应于特定厚度的相应高度的一组第一和第二突起来紧固。

公开(公告)号：US20090147566A1

公开(公告)日：2009-06-11

申请号：US12268581

申请日：2008-11-11

Applicant: Lieh-Chiu Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

Inventor： Lieh-Chiu Lin ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/75 ,  G11C2213/76 ,  G11C2213/79

Abstract: A phase change memory wherein several phase change storage elements are coupled in series to share a single current source. The current provided by the current source is directed by a plurality of switches. To write/read the phase change storage elements, the invention provides techniques to control the current value generated by the current source and controls the states of the switches. The impedance summation of the phase change storage elements vary with the data stored therein.

Abstract translation: 一种相变存储器，其中几个相变存储元件串联耦合以共享单个电流源。 由电流源提供的电流由多个开关引导。 为了写入/读取相变存储元件，本发明提供了控制由当前源产生的当前值并控制开关状态的技术。 相变存储元件的阻抗求和随其中存储的数据而变化。