Abstract:
A method of fabricating a phase change memory device includes the use of first, second and third polishing processes. The first polishing process forms a first contact portion using a first sacrificial layer and the second polishing process forms a phase change material pattern using a second sacrificial layer. After removing the first and second sacrificial layers to expose resultant protruding structures of the first contact portion and the phase change material pattern, a third polishing process is used to polish the resultant protruding structures using an insulation layer as a polishing stopper layer.
Abstract:
The present invention relates to a tag anti-collision Radio Frequency Identification (RFID) system and a method for tag identification. The method for tag identification consists of a first step of initializing a queue (Q) field and storing a prefix of a candidate queue (CQ) field in the queue field; a second step of transmitting a query including the prefix stored in the queue field to the RFID tags, and deleting the transmitted prefix from the queue field; a third step of inserting a prefix, in which prefixes 0 and 1 are inserted into a rear portion of a prefix of a previously transmitted query, into the queue field if two or more tags respond to the previously transmitted prefix and, therefore, the tags cannot be identified, and inserting the prefix of the previously transmitted query into the candidate queue field and deleting an unnecessary prefix stored in the candidate queue if there is no response or only one tag responds with respect to the previously transmitted prefix; and a fourth step of determining whether a prefix stored in the queue field exists, and returning to the second step if there is a prefix stored in the queue field.
Abstract:
A method of manufacturing a complementary metal-oxide semiconductor (CMOS) transistor includes: forming a semiconductor layer in which an n-MOS transistor region and a p-MOS transistor region are defined; forming an insulation layer on the semiconductor layer; forming a conductive layer on the insulation layer; forming a mask pattern exposing the n-MOS transistor region, on the conductive layer; generating a damage region in an upper portion of the conductive layer by implanting impurities in the conductive layer of the n-MOS transistor region using the mask pattern as a mask; removing the mask pattern; removing the damage region; and patterning the conductive layer to form an n-MOS transistor gate and a p-MOS transistor gate. Accordingly, gate thinning and formation of a step between the n-MOS transistor region gate and the p-MOS transistor region gate can be prevented.
Abstract:
Disclosed herein is a system and method for providing a packet network-based MRBT service. In the method, when an originating MSC (110) requests call termination location information from an HLR (120), the HLR transmits an MRBT service request message, including a calling number and a called number, to an MRBT server (140). The MRBT server returns an MRBT service response message, including URL of MRBT content, to the HLR. The HLR transmits a call termination location information response message to the originating MSC, with MRBT service ID information and called party MRBT content URL information included in the call termination location information response message. The originating MSC (110) transmits called party MRBT content URL information to an originating MS (100) on a basis of the MRBT service ID information. The originating MS accesses the MRBT content URL, downloads relevant MRBT content, and plays and stores the MRBT content.
Abstract:
A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. The dielectric layer is etched with a chemical solution such as LAL. Prior to etching, the protruding portion of the electrode is removed or reduced to prevent any bubbles included in the chemical solution from adhering to the electrode. Thus, the chemical solution can etch the dielectric layers without being blocked by any bubbles included in a chemical solution.
Abstract:
Provided is a method of manufacturing a shallow trench isolation (STI) film without voids or added processes. In one embodiment, the method of manufacturing an STI film includes forming a pad oxide pattern film and a silicon nitride film pattern, which define an isolation region, on a semiconductor substrate, and forming a trench by etching the semiconductor substrate to a predetermined depth using the pad oxide film pattern and the silicon nitride film pattern as masks. The resultant semiconductor substrate having the trench may be then dipped in a chemical solution containing ozone to pullback side walls of the silicon nitride film pattern. Afterward, the STI film can be formed by filling the trench with an insulating film.
Abstract:
A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. The dielectric layer is etched with a chemical solution such as LAL. Prior to etching, the protruding portion of the electrode is removed or reduced to prevent any bubbles included in the chemical solution from adhering to the electrode. Thus, the chemical solution can etch the dielectric layers without being blocked by any bubbles included in a chemical solution.
Abstract:
A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. An etchant or chemical solution is applied to the dielectric layer and bubbles in the etchant are prevented from adhering to the electrode. In one embodiment, prior to etching, the protruding portion is covered with a buffer layer to prevent bubbles in the etchant from adhering to the electrode. Thus, the etchant can etch the dielectric layers without being blocked by bubbles included therein.