Method fabricating semiconductor device using multiple polishing processes
    51.
    发明授权
    Method fabricating semiconductor device using multiple polishing processes 有权
    使用多次抛光工艺制造半导体器件的方法

    公开(公告)号:US08168535B2

    公开(公告)日:2012-05-01

    申请号:US13084657

    申请日:2011-04-12

    CPC classification number: H01L45/1683 H01L45/06 H01L45/141

    Abstract: A method of fabricating a phase change memory device includes the use of first, second and third polishing processes. The first polishing process forms a first contact portion using a first sacrificial layer and the second polishing process forms a phase change material pattern using a second sacrificial layer. After removing the first and second sacrificial layers to expose resultant protruding structures of the first contact portion and the phase change material pattern, a third polishing process is used to polish the resultant protruding structures using an insulation layer as a polishing stopper layer.

    Abstract translation: 制造相变存储器件的方法包括使用第一,第二和第三抛光工艺。 第一抛光工艺使用第一牺牲层形成第一接触部分,并且第二抛光工艺使用第二牺牲层形成相变材料图案。 在去除第一和第二牺牲层以暴露第一接触部分的相应突出结构和相变材料图案之后,使用第三抛光工艺来使用绝缘层作为抛光停止层来抛光所得的突出结构。

    Tag anti-collision RFID system and method for tag identification
    52.
    发明授权
    Tag anti-collision RFID system and method for tag identification 有权
    标签防碰撞RFID系统和标签识别方法

    公开(公告)号:US08028910B2

    公开(公告)日:2011-10-04

    申请号:US11817333

    申请日:2005-12-14

    CPC classification number: G06K7/10049 G06K7/0008

    Abstract: The present invention relates to a tag anti-collision Radio Frequency Identification (RFID) system and a method for tag identification. The method for tag identification consists of a first step of initializing a queue (Q) field and storing a prefix of a candidate queue (CQ) field in the queue field; a second step of transmitting a query including the prefix stored in the queue field to the RFID tags, and deleting the transmitted prefix from the queue field; a third step of inserting a prefix, in which prefixes 0 and 1 are inserted into a rear portion of a prefix of a previously transmitted query, into the queue field if two or more tags respond to the previously transmitted prefix and, therefore, the tags cannot be identified, and inserting the prefix of the previously transmitted query into the candidate queue field and deleting an unnecessary prefix stored in the candidate queue if there is no response or only one tag responds with respect to the previously transmitted prefix; and a fourth step of determining whether a prefix stored in the queue field exists, and returning to the second step if there is a prefix stored in the queue field.

    Abstract translation: 本发明涉及标签防碰撞射频识别(RFID)系统和标签识别方法。 用于标签识别的方法包括初始化队列(Q)字段并在队列字段中存储候选队列(CQ)字段的前缀的第一步骤; 将包含队列字段中存储的前缀的查询发送到RFID标签的第二步骤,以及从队列字段中删除发送的前缀; 如果两个或更多个标签响应于先前发送的前缀,并且因此标签中插入前缀0和1被插入到先前发送的查询的前缀的后部中的第三步骤, 如果没有响应或只有一个标签相对于先前发送的前缀进行响应,则不能识别先前发送的查询的前缀到候选队列字段并删除存储在候选队列中的不必要的前缀; 以及确定存储在队列字段中的前缀是否存在的第四步骤,如果存在队列字段中存在前缀,则返回到第二步。

    METHOD OF MANUFACTURING CMOS TRANSISTOR
    53.
    发明申请
    METHOD OF MANUFACTURING CMOS TRANSISTOR 审中-公开
    制造CMOS晶体管的方法

    公开(公告)号:US20100178754A1

    公开(公告)日:2010-07-15

    申请号:US12479112

    申请日:2009-06-05

    Abstract: A method of manufacturing a complementary metal-oxide semiconductor (CMOS) transistor includes: forming a semiconductor layer in which an n-MOS transistor region and a p-MOS transistor region are defined; forming an insulation layer on the semiconductor layer; forming a conductive layer on the insulation layer; forming a mask pattern exposing the n-MOS transistor region, on the conductive layer; generating a damage region in an upper portion of the conductive layer by implanting impurities in the conductive layer of the n-MOS transistor region using the mask pattern as a mask; removing the mask pattern; removing the damage region; and patterning the conductive layer to form an n-MOS transistor gate and a p-MOS transistor gate. Accordingly, gate thinning and formation of a step between the n-MOS transistor region gate and the p-MOS transistor region gate can be prevented.

    Abstract translation: 制造互补金属氧化物半导体(CMOS)晶体管的方法包括:形成其中限定了n-MOS晶体管区域和p-MOS晶体管区域的半导体层; 在所述半导体层上形成绝缘层; 在绝缘层上形成导电层; 在所述导电层上形成暴露所述n-MOS晶体管区域的掩模图案; 通过使用掩模图案作为掩模在n-MOS晶体管区域的导电层中注入杂质,在导电层的上部产生损伤区域; 去除掩模图案; 去除损伤区域; 以及图案化导电层以形成n-MOS晶体管栅极和p-MOS晶体管栅极。 因此,可以防止栅极间化和在n-MOS晶体管区域栅极和p-MOS晶体管区域栅极之间形成台阶。

    SYSTEM AND METHOD FOR PROVIDING PACKET NETWORK-BASED MULTIMEDIA RINGBACK TONE SERVICE
    54.
    发明申请
    SYSTEM AND METHOD FOR PROVIDING PACKET NETWORK-BASED MULTIMEDIA RINGBACK TONE SERVICE 有权
    用于提供基于分组网络的多媒体铃声服务的系统和方法

    公开(公告)号:US20100080149A1

    公开(公告)日:2010-04-01

    申请号:US12599399

    申请日:2008-05-08

    CPC classification number: H04M3/42017 H04W4/16

    Abstract: Disclosed herein is a system and method for providing a packet network-based MRBT service. In the method, when an originating MSC (110) requests call termination location information from an HLR (120), the HLR transmits an MRBT service request message, including a calling number and a called number, to an MRBT server (140). The MRBT server returns an MRBT service response message, including URL of MRBT content, to the HLR. The HLR transmits a call termination location information response message to the originating MSC, with MRBT service ID information and called party MRBT content URL information included in the call termination location information response message. The originating MSC (110) transmits called party MRBT content URL information to an originating MS (100) on a basis of the MRBT service ID information. The originating MS accesses the MRBT content URL, downloads relevant MRBT content, and plays and stores the MRBT content.

    Abstract translation: 本文公开了一种用于提供基于分组网络的MRBT服务的系统和方法。 在该方法中,当起始MSC(110)从HLR(120)请求呼叫终止位置信息时,HLR向MRBT服务器(140)发送包括呼叫号码和被叫号码的MRBT服务请求消息。 MRBT服务器向HLR返回包括MRBT内容的URL的MRBT服务响应消息。 HLR向起始MSC发送呼叫终止位置信息响应消息,其中包括在呼叫终止位置信息响应消息中的MRBT服务ID信息和被叫方MRBT内容URL信息。 始发MSC(110)基于MRBT服务ID信息向主叫MS(100)发送被叫方MRBT内容URL信息。 始发MS访问MRBT内容URL,下载相关MRBT内容,并播放和存储MRBT内容。

    ETCHING METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    55.
    发明申请
    ETCHING METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
    用于制造半导体器件的蚀刻方法

    公开(公告)号:US20080102595A1

    公开(公告)日:2008-05-01

    申请号:US11969105

    申请日:2008-01-03

    CPC classification number: H01L28/91 H01L21/31111

    Abstract: A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. The dielectric layer is etched with a chemical solution such as LAL. Prior to etching, the protruding portion of the electrode is removed or reduced to prevent any bubbles included in the chemical solution from adhering to the electrode. Thus, the chemical solution can etch the dielectric layers without being blocked by any bubbles included in a chemical solution.

    Abstract translation: 提供具有电介质层和从电介质层的顶表面部分突出的电极的晶片。 用诸如LAL的化学溶液蚀刻电介质层。 在蚀刻之前,电极的突出部分被去除或减少,以防止化学溶液中包含的任何气泡粘附到电极上。 因此,化学溶液可以蚀刻介电层而不被包含在化学溶液中的任何气泡所阻挡。

    Method of manufacturing void-free shallow trench isolation layer
    56.
    发明申请
    Method of manufacturing void-free shallow trench isolation layer 审中-公开
    无孔浅沟槽隔离层的制造方法

    公开(公告)号:US20050079682A1

    公开(公告)日:2005-04-14

    申请号:US10961908

    申请日:2004-10-08

    CPC classification number: H01L21/76232

    Abstract: Provided is a method of manufacturing a shallow trench isolation (STI) film without voids or added processes. In one embodiment, the method of manufacturing an STI film includes forming a pad oxide pattern film and a silicon nitride film pattern, which define an isolation region, on a semiconductor substrate, and forming a trench by etching the semiconductor substrate to a predetermined depth using the pad oxide film pattern and the silicon nitride film pattern as masks. The resultant semiconductor substrate having the trench may be then dipped in a chemical solution containing ozone to pullback side walls of the silicon nitride film pattern. Afterward, the STI film can be formed by filling the trench with an insulating film.

    Abstract translation: 提供了一种制造没有空隙或附加工艺的浅沟槽隔离(STI)膜的方法。 在一个实施例中,制造STI膜的方法包括在半导体衬底上形成限定隔离区的衬垫氧化物图案膜和氮化硅膜图案,并且通过使用以下方式将半导体衬底蚀刻到预定深度来形成沟槽 衬垫氧化膜图案和氮化硅膜图案作为掩模。 然后将具有沟槽的所得半导体衬底浸入含有臭氧的化学溶液中以拉回氮化硅膜图案的侧壁。 之后,可以通过用绝缘膜填充沟槽来形成STI膜。

    Etching method for manufacturing semiconductor device
    57.
    发明申请
    Etching method for manufacturing semiconductor device 失效
    蚀刻方法制造半导体器件

    公开(公告)号:US20050064674A1

    公开(公告)日:2005-03-24

    申请号:US10763356

    申请日:2004-01-23

    CPC classification number: H01L28/91 H01L21/31111

    Abstract: A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. The dielectric layer is etched with a chemical solution such as LAL. Prior to etching, the protruding portion of the electrode is removed or reduced to prevent any bubbles included in the chemical solution from adhering to the electrode. Thus, the chemical solution can etch the dielectric layers without being blocked by any bubbles included in a chemical solution.

    Abstract translation: 提供具有电介质层和从电介质层的顶表面部分突出的电极的晶片。 用诸如LAL的化学溶液蚀刻电介质层。 在蚀刻之前,电极的突出部分被去除或减少,以防止化学溶液中包含的任何气泡粘附到电极上。 因此,化学溶液可以蚀刻介电层而不被包含在化学溶液中的任何气泡所阻挡。

    Etching method for manufacturing semiconductor device
    58.
    发明申请
    Etching method for manufacturing semiconductor device 审中-公开
    蚀刻方法制造半导体器件

    公开(公告)号:US20050026452A1

    公开(公告)日:2005-02-03

    申请号:US10855313

    申请日:2004-05-26

    CPC classification number: H01L28/91 H01L21/31111 H01L27/10852

    Abstract: A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. An etchant or chemical solution is applied to the dielectric layer and bubbles in the etchant are prevented from adhering to the electrode. In one embodiment, prior to etching, the protruding portion is covered with a buffer layer to prevent bubbles in the etchant from adhering to the electrode. Thus, the etchant can etch the dielectric layers without being blocked by bubbles included therein.

    Abstract translation: 提供具有电介质层和从电介质层的顶表面部分突出的电极的晶片。 将蚀刻剂或化学溶液施加到电介质层,并且防止蚀刻剂中的气泡粘附到电极上。 在一个实施例中,在蚀刻之前,突出部分被缓冲层覆盖,以防止蚀刻剂中的气泡粘附到电极上。 因此,蚀刻剂可以蚀刻电介质层而不被其中包含的气泡阻挡。

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