公开(公告)号：US20080173904A1

公开(公告)日：2008-07-24

申请号：US11655856

申请日：2007-01-22

申请人： Ming-Chyi Liu ,  Shih-Chi Fu ,  Yuan-Hung Liu ,  Wei-Chih Chen ,  Chi-Hsin Lo

发明人： Ming-Chyi Liu ,  Shih-Chi Fu ,  Yuan-Hung Liu ,  Wei-Chih Chen ,  Chi-Hsin Lo

IPC分类号： H01L27/148

CPC分类号： H01L27/14636 ,  H01L24/05 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14643 ,  H01L27/14687 ,  H01L2224/05556 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2924/00

摘要： A CMOS image sensor with a bonding pad comprises a semiconductor substrate having a pixel region and a circuit region; a passivation layer having an opening over the semiconductor substrate; and a bonding pad in circuit region, the bonding pad without extending to an upper surface of the passivation layer.

摘要翻译： 具有接合焊盘的CMOS图像传感器包括具有像素区域和电路区域的半导体衬底; 钝化层，其具有在所述半导体衬底上的开口; 以及电路区域中的焊盘，所述接合焊盘不延伸到钝化层的上表面。

公开(公告)号：US07202130B2

公开(公告)日：2007-04-10

申请号：US10775290

申请日：2004-02-10

申请人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Yeur-Luen Tu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Yuan-Hung Liu ,  Chih-Ta Wu ,  Yeur-Luen Tu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： A spacer, a split gate flash memory cell, and related method of forming the same. In one aspect, a composite spacer includes a first spacer insulating layer having a first deposition distribution that varies as a function of a location on a substrate. The composite spacer also includes a second spacer insulating layer having a second deposition distribution that varies in substantial opposition to the first deposition distribution. In another aspect, a composite spacer includes a first spacer insulating layer having a substantially uniform deposition distribution across a surface thereof. The composite spacer also includes a second spacer insulating layer having a varying deposition distribution with a thinner composition in selected regions of the memory cell. In another aspect, a coupling spacer provides for a conductive layer that extends between a floating gate and a substrate insulating layer adjacent a source recessed into the substrate of the memory cell.

摘要翻译： 间隔物，分裂栅极闪存单元及其相关方法。 在一个方面，一种复合间隔物包括具有第一沉积分布的第一间隔绝缘层，其随着基底上的位置而变化。 复合间隔物还包括具有与第一沉积分布基本相反的第二沉积分布的第二间隔绝缘层。 在另一方面，复合间隔物包括在其表面上具有基本均匀的沉积分布的第一间隔绝缘层。 复合间隔物还包括具有在存储单元的选定区域中具有较薄组成的不同沉积分布的第二间隔绝缘层。 在另一方面，耦合间隔物提供导电层，该导电层在浮置栅极和与凹入到存储器单元的衬底中的源极相邻的衬底绝缘层之间延伸。

公开(公告)号：US06218244B1

公开(公告)日：2001-04-17

申请号：US09482757

申请日：2000-01-13

申请人： Bor-Wen Chan ,  Yuan-Hung Liu

发明人： Bor-Wen Chan ,  Yuan-Hung Liu

IPC分类号： H01L218242

CPC分类号： H01L28/92 ,  H01L27/10852

摘要： A method of manufacturing a DRAM capacitor is described. A silicon substrate structure includes an oxide layer over a substrate and a polysilicon layer over the oxide layer. The polysilicon layer also includes a plug that penetrates the oxide layer. A patterned photoresist layer is next formed over the polysilicon layer. Spacers having a low etching rate are formed on the sidewalls of the photoresist layer by carrying out a chemical reaction next to the sidewall of the photoresist layer. A dry etching operation is carried out to etch the unreacted photoresist layer and the polysilicon layer exposed by the openings in the photoresist layer. Using the spacers as an etching mask, a portion of the polysilicon layer under the photoresist layer is removed by continuing the dry etching operation. Lastly, the spacers are removed to form a crown-shaped capacitor.

摘要翻译： 描述制造DRAM电容器的方法。 硅衬底结构包括在衬底上的氧化物层和氧化物层上的多晶硅层。 多晶硅层还包括穿透氧化物层的插塞。 随后在多晶硅层上形成图案化的光致抗蚀剂层。 通过在光致抗蚀剂层的侧壁附近进行化学反应，在光致抗蚀剂层的侧壁上形成具有低蚀刻速率的间隔物。 进行干蚀刻操作以蚀刻由光致抗蚀剂层中的开口暴露的未反应的光致抗蚀剂层和多晶硅层。 使用间隔物作为蚀刻掩模，通过继续干蚀刻操作来除去光致抗蚀剂层下面的多晶硅层的一部分。 最后，去除间隔物以形成冠状电容器。