公开(公告)号：US11211330B2

公开(公告)日：2021-12-28

申请号：US15636245

申请日：2017-06-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H01L23/535 ,  H01L29/786 ,  H01L29/423 ,  H01L29/45 ,  H01L29/417 ,  H01L21/768 ,  H01L27/02 ,  H01L29/49 ,  G06F30/39 ,  G06F30/392 ,  H01L21/8234 ,  H01L21/8238

Abstract: A system and method for efficiently creating layout for a standard cell are described. A standard cell to be used for an integrated circuit uses a full trench silicide strap as drain regions for a pmos transistor and an nmos transistor. Multiple unidirectional routes in metal zero are placed across the standard cell where each route connects to a trench silicide contact. Power and ground connections utilize pins rather than end-to-end rails in the standard cell. Additionally, intermediate nodes are routed in the standard cell with unidirectional routes.

公开(公告)号：US10186510B2

公开(公告)日：2019-01-22

申请号：US15632877

申请日：2017-06-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  G06F17/50

Abstract: A system and method for creating a layout for a vertical gate all around standard cell are described. Metal gate is placed all around two vertical nanowire sheets formed on a silicon substrate. A gate contact is formed on the metal gate between the two vertical nanowire sheets. Gate extension metal (GEM) is placed above the metal gate at least on the gate contact. A via for a gate is formed at a location on the GEM where a local interconnect layer is available to be used for routing a gate connection. Local metal layers are placed for connecting local routes and power connections.

公开(公告)号：US20180315645A1

公开(公告)日：2018-11-01

申请号：US15608749

申请日：2017-05-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76877

Abstract: A system and method for fabricating metal patterns are described. Multiple mandrels are formed on a first polysilicon layer which is on top of a first oxide layer. Each mandrel uses a second polysilicon on top of a first nitride. A spacer oxide and a spacer nitride are formed on the sidewalls of the mandrels to create double spacers. A second oxide layer is deposited followed by removing layers until the first nitride in the mandrels is reached. Areas are etched based on a selected method of multiple available methods until the first oxide layer is etched providing trenches for the metal patterns. Remaining materials on the first oxide layer are removed followed by metal being deposited in the trenches in the first oxide layer.

公开(公告)号：US20180090440A1

公开(公告)日：2018-03-29

申请号：US15275028

申请日：2016-09-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Richard T. Schultz ,  Regina Tien Schmidt ,  Derek P. Peterson ,  Te-Hsuan Chen ,  Elizabeth C. Conrad ,  Catherina Simona Matheis Ionescu ,  Chu-Wen Wang

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  G06F17/50

CPC classification number: H01L23/5286 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/5223 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L28/60 ,  H01L2027/11811

Abstract: Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.

公开(公告)号：US09704995B1

公开(公告)日：2017-07-11

申请号：US15270982

申请日：2016-09-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L29/51

CPC classification number: H01L29/7856 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L2029/7858

Abstract: A system and method for fabricating non-planar devices while managing short channel and heating effects are described. A semiconductor device fabrication process includes forming a non-planar device where the body of the device is insulated from the silicon substrate, but the source and drain regions are not insulated from the silicon substrate. The process builds a local silicon on insulator (SOI) while not insulating area around the source and drain regions from the silicon substrate. A trench is etched a length at least that of a channel length of the device while being bounded by a site for a source region and a site for a drain region. The trench is filled with relatively thick layers to form the local SOI. When nanowires of a gate are residing on top of the layer-filled trench, a second trench is etched into the top layer for depositing gate metal in the second trench.

公开(公告)号：US20140197494A1

公开(公告)日：2014-07-17

申请号：US14217905

申请日：2014-03-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/76801 ,  H01L21/76895 ,  H01L21/76897

Abstract: A semiconductor device fabrication process includes forming insulating mandrels over replacement metal gates on a semiconductor substrate with first gates having sources and drains and at least one second gate being isolated from the first gates. Mandrel spacers are formed around each insulating mandrel. The mandrels and mandrel spacers include the first insulating material. A second insulating layer of the second insulating material is formed over the transistor. One or more first trenches are formed to the sources and drains of the first gates by removing the second insulating material between the insulating mandrels. A second trench is formed to the second gate by removing portions of the first and second insulating materials above the second gate. The first trenches and the second trench are filled with conductive material to form first contacts to the sources and drains of the first gates and a second contact to the second gate.

Abstract translation: 半导体器件制造工艺包括在半导体衬底上的替代金属栅极上形成绝缘心轴，其中第一栅极具有源极和漏极，并且至少一个第二栅极与第一栅极隔离。 在每个绝缘心轴周围形成心轴间隔物。 心轴和心轴间隔件包括第一绝缘材料。 第二绝缘材料的第二绝缘层形成在晶体管的上方。 通过去除绝缘心轴之间的第二绝缘材料，将一个或多个第一沟槽形成到第一栅极的源极和漏极。 通过去除第二栅极上方的第一绝缘材料和第二绝缘材料的部分，形成第二沟槽到第二栅极。 第一沟槽和第二沟槽填充有导电材料，以形成第一栅极的源极和漏极的第一接触以及到第二栅极的第二接触。

公开(公告)号：US20140145342A1

公开(公告)日：2014-05-29

申请号：US13686184

申请日：2012-11-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Richard T. Schultz ,  Omid Rowhani ,  Charles P. Tung

IPC: H01L21/3213 ,  H01L23/48

CPC classification number: H01L23/48 ,  G03F7/0035 ,  G03F7/70466 ,  H01L21/31144 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: Methods, a computer readable medium, and an apparatus are provided. A method includes and the computer readable medium is configured for decomposing an overall pattern into a first mask pattern that includes a power rail base pattern and into a second mask pattern, and generating on the second mask pattern a power rail insert pattern that is at least partially aligned with the power rail base pattern of the first mask pattern. The apparatus is produced by photolithography using photolithographic masks generated by the method.

Abstract translation: 提供了方法，计算机可读介质和装置。 一种方法包括并且所述计算机可读介质被配置用于将整体图案分解为包括电力轨基座图案并进入第二掩模图案的第一掩模图案，并且在所述第二掩模图案上生成至少为电动轨迹插入图案 部分地与第一掩模图案的电源轨基座图案对准。 该装置通过使用通过该方法产生的光刻掩模的光刻制造。