公开(公告)号：US20140237276A1

公开(公告)日：2014-08-21

申请号：US13767897

申请日：2013-02-15

Applicant: APPLE INC.

Inventor： Erik P. Machnicki ,  Brian P. Lilly ,  Gurjeet S. Saund ,  Sukalpa Biswas

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: Various method and apparatus embodiments for selecting tunable operating parameters in an integrated circuit (IC) are disclosed. In one embodiment, an IC includes a number of various functional blocks each having a local management circuit. The IC also includes a global management unit coupled to each of the functional blocks having a local management circuit. The management unit is configured to determine the operational state of the IC based on the respective operating states of each of the functional blocks. Responsive to determining the operational state of the IC, the management unit may provide indications of the same to the local management circuit of each of the functional blocks. The local management circuit for each of the functional blocks may select one or more tunable parameters based on the operational state determined by the management unit.

Abstract translation: 公开了用于在集成电路（IC）中选择可调工作参数的各种方法和装置实施例。 在一个实施例中，IC包括多个各自具有本地管理电路的功能块。 IC还包括耦合到具有本地管理电路的每个功能块的全局管理单元。 管理单元被配置为基于每个功能块的各自的操作状态来确定IC的操作状态。 响应于确定IC的操作状态，管理单元可以向每个功能块的本地管理电路提供相同的指示。 每个功能块的本地管理电路可以基于由管理单元确定的操作状态来选择一个或多个可调参数。

公开(公告)号：US20140223049A1

公开(公告)日：2014-08-07

申请号：US13760795

申请日：2013-02-06

Applicant: APPLE INC.

Inventor： Deniz Balkan ,  Gurjeet S. Saund ,  Shu-Yi Yu

IPC: G06F13/42

CPC classification number: G06F13/4027 ,  G06F11/0766 ,  G06F11/0772

Abstract: Embodiments of a bridge circuit and system are disclosed that may allow for converting transactions from one communication protocol to another. The bridge circuit may be coupled to a first bus employing a first communication protocol, and a second bus employing a second communication protocol. The bridge circuit may be configured to convert transactions from the first communication protocol to the second communication protocol, and convert transaction from the second communication protocol to the first communication protocol. In one embodiment, the bridge circuit may be further configured to flag transactions that cannot be converted from the second communication protocol to the first communication protocol. In a further embodiment, an error circuit coupled to the bridge circuit may be configured to detect flagged transactions.

Abstract translation: 公开了桥接电路和系统的实施例，其可以允许将事务从一个通信协议转换到另一个通信协议。 桥接电路可以耦合到采用第一通信协议的第一总线，以及采用第二通信协议的第二总线。 桥接电路可以被配置为将事务从第一通信协议转换为第二通信协议，并将事务从第二通信协议转换为第一通信协议。 在一个实施例中，桥接电路可以被进一步配置为标记不能从第二通信协议转换到第一通信协议的事务。 在另一个实施例中，耦合到桥接电路的错误电路可以被配置为检测标记的事务。

公开(公告)号：US20140189411A1

公开(公告)日：2014-07-03

申请号：US13733775

申请日：2013-01-03

Applicant: APPLE INC.

Inventor： Muditha Kanchana ,  Gurjeet S. Saund ,  Harshavardhan Kaushikkar ,  Erik P. Machnicki ,  Seye Ewedemi

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C5/144 ,  Y02D10/14

Abstract: Techniques are disclosed relating to reducing power consumption in integrated circuits. In one embodiment, an apparatus includes a cache having a set of tag structures and a power management unit. The power management unit is configured to power down a duplicate set of tag structures in responsive to the cache being powered down. In one embodiment, the cache is configured to provide, to the power management unit, an indication of whether the cache includes valid data. In such an embodiment, the power management unit is configured to power down the cache in response to the cache indicating that the cache does not include valid data. In some embodiments, the duplicate set of tag structures is located within a coherence point configured to maintain coherency between the cache and a memory.

Abstract translation: 公开了关于降低集成电路中的功耗的技术。 在一个实施例中，一种装置包括具有一组标签结构的缓存和电源管理单元。 功率管理单元被配置为响应于被断电的高速缓存而将重复的一组标签结构断电。 在一个实施例中，高速缓存被配置为向电力管理单元提供高速缓存是否包括有效数据的指示。 在这样的实施例中，功率管理单元被配置为响应于缓存指示高速缓存不包括有效数据的高速缓存来关闭高速缓存。 在一些实施例中，重复的标签结构集合位于被配置为保持高速缓存和存储器之间的一致性的相干点内。

公开(公告)号：US20140181571A1

公开(公告)日：2014-06-26

申请号：US13726437

申请日：2012-12-24

Applicant: APPLE INC.

Inventor： Jason M. Kassoff ,  Kevin C. Wong ,  Brian P. Lilly ,  Gurjeet S. Saund

IPC: G06F1/06

CPC classification number: G06F5/06 ,  G06F13/38 ,  G06F13/382

Abstract: Systems and methods for managing fast to slow links in a bus fabric. A pair of link interface units connect agents with a clock mismatch. Each link interface unit includes an asynchronous FIFO for storing transactions that are sent over the clock domain crossing. When the command for a new transaction is ready to be sent while data for the previous transaction is still being sent, the link interface unit prevents the last data beat of the previous transaction from being sent. Instead, after a delay of one or more clock cycles, the last data beat overlaps with the command of the new transaction.

Abstract translation: 用于管理总线结构中快速到慢速链接的系统和方法。 一对链路接口单元连接具有时钟不匹配的代理。 每个链路接口单元包括用于存储通过时钟域穿越发送的事务的异步FIFO。 当新的事务的命令准备好发送，而前一个事务的数据仍然被发送时，链接接口单元阻止发送先前事务的最后数据节拍。 相反，在一个或多个时钟周期的延迟之后，最后的数据跳转与新事务的命令重叠。