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    Methods and apparatus for reduced overhead data transfer with a shared ring buffer
    51.
    发明授权
    Methods and apparatus for reduced overhead data transfer with a shared ring buffer 有权

    公开(公告)号：US10430352B1

    公开(公告)日：2019-10-01

    申请号：US15984153

    申请日：2018-05-18

    Applicant: Apple Inc.

    Inventor： Karan Sanghi ,  Saurabh Garg ,  Vladislav V. Petkov

    IPC: G06F13/16 ,  G06F12/0831 ,  G06F15/167 ,  G06F15/173

    Abstract: Methods and apparatus for reducing bus overhead with virtualized transfer rings. The Inter-Processor Communications (IPC) bus uses a ring buffer (e.g., a so-called Transfer Ring (TR)) to provide Direct Memory Access (DMA)-like memory access between processors. However, performing small transactions within the TR inefficiently uses bus overhead. A Virtualized Transfer Ring (VTR) is a null data structure that doesn't require any backing memory allocation. A processor servicing a VTR data transfer includes the data payload as part of an optional header/footer data structure within a completion ring (CR).

    Methods and apparatus for aggregating packet transfer over a virtual bus interface
    52.
    发明授权
    Methods and apparatus for aggregating packet transfer over a virtual bus interface 有权

    公开(公告)号：US10372637B2

    公开(公告)日：2019-08-06

    申请号：US15721485

    申请日：2017-09-29

    Applicant: Apple Inc.

    Inventor： Radha Kumar Pulyala ,  Saurabh Garg ,  Karan Sanghi

    IPC: G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F13/28

    Abstract: Methods and apparatus for data aggregation and multiplexing of one or more virtual bus interfaces via a physical bus interface. Various disclosed embodiments are configured to: (i) multiplex multiple logical interfaces over a single physical interface, (ii) exchange session management and logical interface control, (iii) manage flow control, (iv) provide “hints” about the data (e.g., metadata), and/or (v) pad data packets. In one particular implementation, the methods and apparatus are configured for use within a wireless-enabled portable electronic device, such as for example a cellular-enabled smartphone, and make use of one or more features of a high-speed serialized physical bus interface.

    Methods and apparatus for reduced-latency data transmission with an inter-processor communication link between independently operable processors
    53.
    发明授权
    Methods and apparatus for reduced-latency data transmission with an inter-processor communication link between independently operable processors 有权

    公开(公告)号：US10331612B1

    公开(公告)日：2019-06-25

    申请号：US15865638

    申请日：2018-01-09

    Applicant: Apple Inc.

    Inventor： Vladislav Petkov ,  Saurabh Garg ,  Karan Sanghi ,  Haining Zhang

    IPC: G06F15/17 ,  G06F13/42 ,  H04W4/80

    CPC classification number: G06F15/17 ,  G06F13/4221 ,  H04W4/80

    Abstract: Methods and apparatus for data transmissions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, the IPC link is configured to enable an independently operable processor to transact data to another independently operable processor, while obviating transactions (such as via direct memory access) by encapsulating a payload within a data structure. For example, a host processor may insert the payload into a transfer descriptor (TD), and transmit the TD to a peripheral processor. The host processor may also include a head index and/or a tail index within a doorbell message sent to the peripheral processor, obviating another access of memory. The peripheral processor may perform similar types of transactions via a completion descriptor (CD) sent to the host processor. In some variants, the peripheral may be a Bluetooth-enabled device optimized for low-latency, low-power, and/or low-throughput transactions.

    METHODS AND APPARATUS FOR RUNNING AND BOOTING AN INTER-PROCESSOR COMMUNICATION LINK BETWEEN INDEPENDENTLY OPERABLE PROCESSORS
    54.
    发明申请
    METHODS AND APPARATUS FOR RUNNING AND BOOTING AN INTER-PROCESSOR COMMUNICATION LINK BETWEEN INDEPENDENTLY OPERABLE PROCESSORS 审中-公开

    公开(公告)号：US20190086993A1

    公开(公告)日：2019-03-21

    申请号：US16133543

    申请日：2018-09-17

    Applicant: Apple Inc.

    Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

    IPC: G06F1/32 ,  G06F13/42

    Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

    METHODS AND APPARATUS FOR TRANSMITTING TIME SENSITIVE DATA OVER A TUNNELED BUS INTERFACE
    55.
    发明申请
    METHODS AND APPARATUS FOR TRANSMITTING TIME SENSITIVE DATA OVER A TUNNELED BUS INTERFACE 审中-公开

    公开(公告)号：US20190042525A1

    公开(公告)日：2019-02-07

    申请号：US15720603

    申请日：2017-09-29

    Applicant: Apple Inc.

    Inventor： Jason McElrath ,  Karan Sanghi ,  Saurabh Garg

    IPC: G06F13/42 ,  G06F9/46 ,  G06F13/16

    CPC classification number: G06F13/4291 ,  G06F9/466 ,  G06F9/546 ,  G06F13/1673 ,  G06F13/3625 ,  H04L25/00 ,  H04W72/12 ,  H04W84/042

    Abstract: Methods and apparatus for time sensitive data transfer between logical domains. In one embodiment, an user equipment (UE) device has an application processor (AP) coupled to a baseband processor (BB) that operate independently of one another normally, but may cooperate in limited hybrid use scenarios. For example, the BB receives audio packets via a cellular network that are converted to pulse code modulated (PCM) digital audio to be played by the AP. Unfortunately, since the AP and the BB are independently clocked, they will experience some clock drift. As a result, the audio playback may have undesirable artifacts if the drift is not otherwise compensated for. To these ends, the AP and/or BB determine a relative clock drift and compensate for playback by e.g., adding, padding, or deleting audio samples and/or audio packets. Techniques for handover scenarios are also disclosed.

    METHODS AND APPARATUS FOR MANAGING POWER WITH AN INTER-PROCESSOR COMMUNICATION LINK BETWEEN INDEPENDENTLY OPERABLE PROCESSORS
    60.
    发明申请
    METHODS AND APPARATUS FOR MANAGING POWER WITH AN INTER-PROCESSOR COMMUNICATION LINK BETWEEN INDEPENDENTLY OPERABLE PROCESSORS 有权
    用独立可操作的处理器之间的处理器间通信链路管理功率的方法和装置

    公开(公告)号：US20160103480A1

    公开(公告)日：2016-04-14

    申请号：US14879027

    申请日：2015-10-08

    Applicant: Apple Inc.

    Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

    IPC: G06F1/32 ,  G06F13/42

    CPC classification number: G06F1/3293 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F11/1417 ,  G06F11/1471 ,  G06F11/1474 ,  G06F13/4282 ,  G06F2201/805 ,  G06F2201/87 ,  Y02D10/122 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171

    Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

    Abstract translation: 两个（或多个）可独立操作的处理器之间的处理器间通信（IPC）链接的方法和装置。 在一个方面，IPC协议基于用于运行时处理的“共享”存储器接口（即，独立可操作的处理器每个共享（虚拟或物理上）公共存储器接口）。 在另一方面，IPC通信链路被配置为支持在引导序列期间使用的主机驱动的引导协议，以在外围设备和主处理器之间建立基本通信路径。 本文描述的各种其他实施例包括睡眠过程（如针对主机和外围处理器分别定义的）和错误处理。

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