公开(公告)号：US20080070384A1

公开(公告)日：2008-03-20

申请号：US11521850

申请日：2006-09-14

申请人： Anand S. Murthy ,  Jeffrey L. Armstrong ,  Dennis G. Hanken

发明人： Anand S. Murthy ,  Jeffrey L. Armstrong ,  Dennis G. Hanken

IPC分类号： H01L21/00

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

摘要： A method to form a strain-inducing epitaxial film is described. In one embodiment, the strain-inducing epitaxial film is a three-component epitaxial film comprising atoms from a parent film, charge-neutral lattice-substitution atoms and charge-carrier dopant impurity atoms. In another embodiment, the strain-inducing epitaxial film is formed by a multiple deposition/etch cycle sequence involving hydrogenated amorphous silicon, followed by charge carrier dopant and charge-neutral lattice-forming impurity atom implant steps and, finally, a kinetically-driven crystallization process.

摘要翻译： 描述形成应变诱导外延膜的方法。 在一个实施例中，应变诱导外延膜是包含来自母膜的原子，电荷 - 中性晶格取代原子和电荷 - 载流子掺杂杂质原子的三组分外延膜。 在另一个实施例中，应变诱导外延膜通过涉及氢化非晶硅的多次沉积/蚀刻循环序列形成，随后是电荷载流子掺杂剂和电荷 - 中性晶格形成杂质原子注入步骤，最后是动力学驱动的结晶 处理。

公开(公告)号：US06933589B2

公开(公告)日：2005-08-23

申请号：US10917165

申请日：2004-08-11

申请人： Anand S. Murthy ,  Boyan Boyanov ,  Ravindra Soman ,  Robert S. Chau

发明人： Anand S. Murthy ,  Boyan Boyanov ,  Ravindra Soman ,  Robert S. Chau

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/45 ,  H01L29/78 ,  H01L31/117 ,  H01L31/0288

CPC分类号： H01L29/66477 ,  H01L21/2254 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： Transistors are manufactured by growing germanium source and drain regions, implanting dopant impurities into the germanium, and subsequently annealing the source and drain regions so that the dopant impurities diffuse through the germanium. The process is simpler than a process wherein germanium is insitu doped with p-type or n-type impurities. The dopant impurities diffuse easily through the germanium but not easily through underlying silicon, so that an interface between the germanium and silicon acts as a diffusion barrier and ensures positioning of the dopant atoms in the regions of the device where they improve transistor performance.

公开(公告)号：US06605498B1

公开(公告)日：2003-08-12

申请号：US10112170

申请日：2002-03-29

申请人： Anand S. Murthy ,  Brian S. Doyle ,  Brian E. Roberds

发明人： Anand S. Murthy ,  Brian S. Doyle ,  Brian E. Roberds

IPC分类号： H01L21336

CPC分类号： H01L29/66636 ,  H01L29/1054 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/802

摘要： A stressed channel is formed in a PMOS transistor by etching a recess and subsequently backfilling the recess with an epitaxially formed alloy of silicon, germanium, and an n-type dopant. The alloy has the same crystal structure as the underlying silicon, but the spacing of the crystal is larger, due to the inclusion of the germanium. An NMOS transistor can be formed by including carbon instead of germanium.

摘要翻译： 通过蚀刻凹槽并随后用外延形成的硅，锗和n型掺杂剂的合金回填凹陷，在PMOS晶体管中形成应力通道。 该合金具有与下面的硅相同的晶体结构，但是由于包含锗，晶体的间距较大。 可以通过包括碳代替锗来形成NMOS晶体管。

公开(公告)号：US07951673B2

公开(公告)日：2011-05-31

申请号：US12713432

申请日：2010-02-26

申请人： Nick Lindert ,  Suman Datta ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Justin K. Brask ,  Robert S. Chau ,  Mark Bohr ,  Anand S. Murthy

发明人： Nick Lindert ,  Suman Datta ,  Jack Kavalieros ,  Mark L. Doczy ,  Matthew V. Metz ,  Justin K. Brask ,  Robert S. Chau ,  Mark Bohr ,  Anand S. Murthy

IPC分类号： H01L29/76

CPC分类号： H01L29/7833 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

摘要： A gate structure may be utilized as a mask to form source and drain regions. Then the gate structure may be removed to form a gap and spacers may be formed in the gap to define a trench. In the process of forming a trench into the substrate, a portion of the source drain region is removed. Then the substrate is filled back up with an epitaxial material and a new gate structure is formed thereover. As a result, more abrupt source drain junctions may be achieved.

摘要翻译： 栅极结构可以用作掩模以形成源区和漏区。 然后可以去除栅极结构以形成间隙，并且可以在间隙中形成间隔物以限定沟槽。 在将沟槽形成衬底的过程中，去除源极漏极区的一部分。 然后用外延材料填充衬底，并在其上形成新的栅极结构。 结果，可以实现更突然的源极漏极结。

公开(公告)号：US07338873B2

公开(公告)日：2008-03-04

申请号：US11437569

申请日：2006-05-19

申请人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

发明人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2022 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

公开(公告)号：US06972228B2

公开(公告)日：2005-12-06

申请号：US10387623

申请日：2003-03-12

申请人： Brian S. Doyle ,  Anand S. Murthy ,  Robert S. Chau

发明人： Brian S. Doyle ,  Anand S. Murthy ,  Robert S. Chau

IPC分类号： H01L21/20 ,  H01L29/12 ,  H01S5/34 ,  H01L21/8242

CPC分类号： H01L29/66795 ,  B82Y10/00 ,  B82Y20/00 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0262 ,  H01L29/125 ,  H01S5/341

摘要： A method is described for forming an element of a microelectronic circuit. A sacrificial layer is formed on an upper surface of a support layer. The sacrificial layer is extremely thin and uniform. A height-defining layer is then formed on the sacrificial layer, whereafter the sacrificial layer is etched away so that a well-defined gap is left between an upper surface of the support layer and a lower surface of the height-defining layer. A monocrystalline semiconductor material is then selectively grown from a nucleation silicon site through the gap. The monocrystalline semiconductor material forms a monocrystalline layer having a thickness corresponding to the thickness of the original sacrificial layer.

摘要翻译： 描述了形成微电子电路的元件的方法。 牺牲层形成在支撑层的上表面上。 牺牲层非常薄而均匀。 然后在牺牲层上形成高度限定层，然后牺牲层被蚀刻掉，使得在支撑层的上表面和高度限定层的下表面之间留下明确限定的间隙。 然后从成核硅部位通过间隙选择性地生长单晶半导体材料。 单晶半导体材料形成具有对应于原始牺牲层的厚度的厚度的单晶层。

公开(公告)号：US08642413B2

公开(公告)日：2014-02-04

申请号：US11521850

申请日：2006-09-14

申请人： Anand S. Murthy ,  Jeffrey L. Armstrong ,  Dennis G. Hanken

发明人： Anand S. Murthy ,  Jeffrey L. Armstrong ,  Dennis G. Hanken

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

摘要： A method to form a strain-inducing epitaxial film is described. In one embodiment, the strain-inducing epitaxial film is a three-component epitaxial film comprising atoms from a parent film, charge-neutral lattice-substitution atoms and charge-carrier dopant impurity atoms. In another embodiment, the strain-inducing epitaxial film is formed by a multiple deposition/etch cycle sequence involving hydrogenated amorphous silicon, followed by charge carrier dopant and charge-neutral lattice-forming impurity atom implant steps and, finally, a kinetically-driven crystallization process.

摘要翻译： 描述形成应变诱导外延膜的方法。 在一个实施例中，应变诱导外延膜是包含来自母膜的原子，电荷 - 中性晶格取代原子和电荷 - 载流子掺杂杂质原子的三组分外延膜。 在另一个实施例中，应变诱导外延膜通过涉及氢化非晶硅的多次沉积/蚀刻循环序列形成，随后是电荷载流子掺杂剂和电荷 - 中性晶格形成杂质原子注入步骤，最后是动力学驱动的结晶 处理。

公开(公告)号：US20100133595A1

公开(公告)日：2010-06-03

申请号：US12700637

申请日：2010-02-04

申请人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

发明人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

IPC分类号： H01L29/78

CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2022 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

摘要翻译： 体现本发明的微电子结构包括具有高导电性的源极/漏极延伸的场效应晶体管（FET）。 形成这种高导电的源极/漏极延伸部分包括形成钝化的凹槽，其通过掺杂材料的外延沉积而填充以形成源极/漏极结。 凹部包括在栅极结构的一部分下面的横向延伸的区域。 这种横向延伸部可以位于与栅电极的垂直侧壁相邻的侧壁间隔物的下面，或者可以进一步延伸到FET的沟道部分中，使得侧向凹槽位于栅极结构的栅电极部分的下方。 在一个实施例中，通过相对掺杂材料的双层的原位外延沉积来将凹部反向填充。 以这种方式，实现了非常突然的结，其提供相对较低的电阻源极/漏极延伸并进一步提供良好的截止阈值泄漏特性。 替代实施例可以用单导电类型的后填充凹槽来实现。

公开(公告)号：US07494858B2

公开(公告)日：2009-02-24

申请号：US11173660

申请日：2005-06-30

申请人： Mark T. Bohr ,  Steven J. Keating ,  Thomas A. Letson ,  Anand S. Murthy ,  Donald W. O'Neill ,  Willy Rachmady

发明人： Mark T. Bohr ,  Steven J. Keating ,  Thomas A. Letson ,  Anand S. Murthy ,  Donald W. O'Neill ,  Willy Rachmady

IPC分类号： H01L21/336

CPC分类号： H01L29/045 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.

摘要翻译： 实施例是改进的晶体管结构和制造该结构的方法。 特别地，实施例的湿蚀刻形成具有改进的尖端形状的源极和漏极区域，以通过改善短沟道效应的控制，增加饱和电流，改善冶金栅极长度的控制，增加载流子迁移率来提高晶体管的性能 并且在源极和漏极与硅化物之间的界面处降低接触电阻。

公开(公告)号：US20090011565A1

公开(公告)日：2009-01-08

申请号：US12231172

申请日：2008-08-28

申请人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

发明人： Anand S. Murthy ,  Robert S. Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2022 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

摘要翻译： 体现本发明的微电子结构包括具有高导电性的源极/漏极延伸的场效应晶体管（FET）。 形成这种高导电的源极/漏极延伸部分包括形成钝化的凹槽，其通过掺杂材料的外延沉积而填充以形成源极/漏极结。 凹部包括在栅极结构的一部分下面的横向延伸的区域。 这种横向延伸部可以位于与栅电极的垂直侧壁相邻的侧壁间隔物的下面，或者可以进一步延伸到FET的沟道部分中，使得侧向凹槽位于栅极结构的栅电极部分的下方。 在一个实施例中，通过相对掺杂材料的双层的原位外延沉积来将凹部反向填充。 以这种方式，实现了非常突然的结，其提供相对较低的电阻源极/漏极延伸并进一步提供良好的截止阈值泄漏特性。 替代实施例可以用单导电类型的后填充凹槽来实现。