公开(公告)号：US06237104B1

公开(公告)日：2001-05-22

申请号：US09222070

申请日：1998-12-29

申请人： Rino Micheloni ,  Giovanni Campardo ,  Stefano Commodaro ,  Guido Lomazzi

发明人： Rino Micheloni ,  Giovanni Campardo ,  Stefano Commodaro ,  Guido Lomazzi

IPC分类号： G06F1200

CPC分类号： G11C8/18 ,  G11C16/32

摘要： A method and related circuit for adjusting the duration of a pulse synchronization signal for the reading phase of memory cells in electronic memory devices which are integrated on semiconductors are discussed. The pulse synchronization signal is produced by a pulse generator when it detects a logical state commutation on at least one input terminal of a plurality of addressing input terminals of the memory cells. The method produces a logical sum between the signal produced by the generator and a pulse signal having a predetermined duration. The logical sum is used to start up the reading phase.

摘要翻译： 讨论了用于调整集成在半导体上的电子存储器件中的存储器单元的读取阶段的脉冲同步信号的持续时间的方法和相关电路。 当脉冲同步信号检测到存储器单元的多个寻址输入端的至少一个输入端上的逻辑状态换向时，脉冲同步信号由脉冲发生器产生。 该方法产生由发生器产生的信号与具有预定持续时间的脉冲信号之间的逻辑和。 逻辑和用于启动读取阶段。

公开(公告)号：US06181602B2

公开(公告)日：2001-01-30

申请号：US09322460

申请日：1999-05-28

申请人： Giovanni Campardo ,  Rino Micheloni ,  Alfonso Maurelli

发明人： Giovanni Campardo ,  Rino Micheloni ,  Alfonso Maurelli

IPC分类号： G11C1606

CPC分类号： G11C16/28 ,  G11C7/06 ,  G11C7/062

摘要： A method for reading memory cells that includes supplying simultaneously two memory cells, both storing a respective unknown charge condition; generating two electrical quantities, each correlated to a respective charge condition of the respective memory cell; comparing the two electrical quantities with each other; and generating a two-bit signal on the basis of the result of the comparison. A reading circuit includes a two-input comparator having two branches in parallel, each branch being connected to a respective memory cell by a current/voltage converter. Both the two-input comparator and the current/voltage converter comprise low threshold transistors.

摘要翻译： 一种用于读取存储单元的方法，包括同时提供两个存储相应未知充电条件的存储器单元; 产生两个电量，每个电量与相应存储器单元的相应充电条件相关; 将两个电量相互比较; 并根据比较结果产生2位信号。 读取电路包括并联的两个分支的双输入比较器，每个分支通过电流/电压转换器连接到相应的存储单元。 双输入比较器和电流/电压转换器均包括低阈值晶体管。

公开(公告)号：US08694849B1

公开(公告)日：2014-04-08

申请号：US13330573

申请日：2011-12-19

申请人： Rino Micheloni ,  Alessia Marelli ,  Peter Z. Onufryk

发明人： Rino Micheloni ,  Alessia Marelli ,  Peter Z. Onufryk

IPC分类号： H03M13/00

CPC分类号： H03M13/2906 ,  G06F11/1048 ,  G06F11/1076 ,  H03M13/152 ,  H03M13/19

摘要： A data storage device stores a data unit in a memory page of a storage block along with an error correction code unit for the data unit. Additionally, the data storage device stores an error correction code unit for the data unit in a memory page of another storage block. In various embodiments, one or both of the error correction code units form an error correction code for correcting data bit errors in the data unit. Because the memory page containing the data unit does not have a storage capacity for simultaneously storing the error correction code and the data unit, the data storage device is capable of correcting a greater number of data bit errors in the data unit by using the error correction code in comparison to using an error correction code that would fit in the memory page.

摘要翻译： 数据存储装置将数据单元与数据单元的纠错码单元一起存储在存储块的存储器页中。 此外，数据存储装置将用于数据单元的纠错码单元存储在另一存储块的存储器页中。 在各种实施例中，纠错码单元中的一个或两个形成用于校正数据单元中的数据位错误的纠错码。 由于包含数据单元的存储器页面不具有用于同时存储纠错码和数据单元的存储容量，所以数据存储装置能够通过使用纠错码来校正数据单元中更大数量的数据位错误 代码与使用适合内存页面的纠错码进行比较。

公开(公告)号：US08397144B1

公开(公告)日：2013-03-12

申请号：US12913716

申请日：2010-10-27

申请人： Christopher I. W. Norrie ,  Alessia Marelli ,  Rino Micheloni ,  Peter Z. Onufryk

发明人： Christopher I. W. Norrie ,  Alessia Marelli ,  Rino Micheloni ,  Peter Z. Onufryk

IPC分类号： H03M13/00

CPC分类号： H03M13/6566 ,  H03M13/152 ,  H03M13/1555 ,  H03M13/6561

摘要： In various embodiments, a data correction system has a data path including search modules. Each of the search modules has a respective bit error capacity for locating a number of data bit errors in a data unit based on a locator polynomial. The data correction system generates a syndrome based on an input data unit, generates a locator polynomial based on the syndrome, and determines a number of data bit errors in the input data unit based on the locator polynomial. Additionally, the data correction system selects one of the search modules having a bit error capacity of at least the number of data bit errors in the input data unit. The selected search module generates an error indicator based on the locator polynomial. The data correction system corrects each data bit error in the input data unit based on the error indicator.

摘要翻译： 在各种实施例中，数据校正系统具有包括搜索模块的数据路径。 每个搜索模块具有用于基于定位多项式定位数据单元中的多个数据位错误的相应位错误容量。 数据校正系统基于输入数据单元产生校正子，根据校正子产生定位多项式，并根据定位多项式确定输入数据单元中的数据位错误数。 此外，数据校正系统选择搜索模块中的一个具有至少输入数据单元中的数据位错误数量的位错误容量。 所选择的搜索模块基于定位多项式生成错误指示符。 数据校正系统根据误差指示器校正输入数据单元中的每个数据位错误。

公开(公告)号：US20090262593A1

公开(公告)日：2009-10-22

申请号：US12248843

申请日：2008-10-09

申请人： Luca Crippa ,  Giancarlo Ragone ,  Miriam Sangalli ,  Rino Micheloni

发明人： Luca Crippa ,  Giancarlo Ragone ,  Miriam Sangalli ,  Rino Micheloni

IPC分类号： G11C7/04 ,  G11C16/06 ,  G11C5/14

CPC分类号： G11C11/5642 ,  G11C7/04 ,  G11C16/30

摘要： A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.

摘要翻译： 电路包括至少一个存储单元，适于根据其电特性的值存储数据，其根据第一变化规律表现出与温度的变化性; 提供电压发生器，用于产生要提供给所述至少一个存储单元的电压以检索存储在其中的数据，所述电压发生器包括适于使所产生的电压取值至少包括至少一组目标值的值的第一装置 一个目标值，对应于要在存储器单元上执行的操作。 电压发生器包括第二装置，用于使得所产生的电压所采取的值根据规定的第二变化规律随温度变化，利用具有所述电特性的补偿电路元件。

公开(公告)号：US07474577B2

公开(公告)日：2009-01-06

申请号：US11444892

申请日：2006-05-31

申请人： Luca Crippa ,  Giancarlo Ragone ,  Miriam Sangalli ,  Rino Micheloni

发明人： Luca Crippa ,  Giancarlo Ragone ,  Miriam Sangalli ,  Rino Micheloni

IPC分类号： G11C7/04

CPC分类号： G11C11/5642 ,  G11C7/04 ,  G11C16/30

摘要： A circuit comprises at least one memory cell adapted to store data in terms of values of an electrical characteristic thereof, which exhibits a variability with temperature according to a first variation law; a voltage generator is provided for generating a voltage to be supplied to the at least one memory cell for retrieving the data stored therein, the voltage generator including first means adapted to cause the generated voltage take a value in a set of target values including at least one target value, corresponding to an operation to be performed on the memory cell. The voltage generator comprises second means for causing the value taken by the generated voltage vary with temperature according to a prescribed second variation law exploiting a compensation circuit element having said electrical characteristic.

摘要翻译： 电路包括至少一个存储单元，适于根据其电特性的值存储数据，其根据第一变化规律表现出与温度的变化性; 提供电压发生器，用于产生要提供给所述至少一个存储单元的电压以检索存储在其中的数据，所述电压发生器包括适于使所产生的电压取值至少包括至少一组目标值的值的第一装置 一个目标值，对应于要在存储器单元上执行的操作。 电压发生器包括第二装置，用于使得所产生的电压所采取的值根据规定的第二变化规律随温度变化，利用具有所述电特性的补偿电路元件。

公开(公告)号：US20080123411A1

公开(公告)日：2008-05-29

申请号：US11821131

申请日：2007-06-21

申请人： Luca Crippa ,  Rino Micheloni

发明人： Luca Crippa ,  Rino Micheloni

IPC分类号： G11C16/04 ,  G11C7/10

CPC分类号： G11C7/1021 ,  G11C7/1039 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2211/5621

摘要： A page buffer for an electrically programmable memory is provided. The page buffer includes a plurality of memory cells, a plurality of distinct programming states defined for each memory cell, corresponding to a number N>=2 of data bits storable in each memory cell, wherein the data bits include at least a first data bits group and a second data bits group and at least one read/program unit having a coupling line operatively associable with selected memory cells. The read/program unit is adapted to at least temporarily store data bits read from or to be written into selected memory cells and comprises programming state change enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential. The programming state change enabling means comprises reading means for retrieving, from the selected memory cell, an indication of an existing data value already stored in the second group of data bits, receiving means for receiving an indication of a target data value to be stored in the first group of data bits of the selected memory cell, combining means activatable during a combining phase for combining the indication of the existing data value with the indication of the received target data value, so as to obtain a modified indication corresponding to a target programming state for the memory cell and conditioning means for causing a potential of the coupling line to take the program enabling potential or the program inhibition potential depending on the modified indication. The combining means includes a coupling electrical path between the reading means and the receiving means, said coupling electrical line being kept isolated from the coupling electrical path during said combining phase.

摘要翻译： 提供了用于电可编程存储器的页面缓冲器。 页面缓冲器包括多个存储器单元，对于每个存储器单元定义的多个不同的编程状态，对应于可存储在每个存储器单元中的数据位数N> = 2，其中数据位至少包括第一数据位 组和第二数据位组以及至少一个具有与所选存储单元可操作地相关联的耦合线的读/写单元。 读取/编程单元适于至少临时存储从或将被写入所选择的存储单元中的数据位，并且包括编程状态改变使能装置，用于通过使所述耦合线选择性地启用所选存储单元的编程状态的改变 在一个能够实现潜力和程序禁止潜力的程序中。 编程状态改变使能装置包括读取装置，用于从所选择的存储器单元检索已经存储在第二组数据位中的现有数据值的指示，接收装置，用于接收要存储的目标数据值的指示 所选择的存储器单元的第一组数据位，在组合阶段可激活的组合装置，用于组合现有数据值的指示与接收到的目标数据值的指示，以便获得对应于目标编程的修改指示 用于存储单元的状态和调节装置，用于使耦合线的电位取决于经修改的指示使能电位或程序禁止电位。 组合装置包括在读取装置和接收装置之间的耦合电路，所述耦合电线在所述组合阶段期间与耦合电路保持隔离。

公开(公告)号：US20070053227A1

公开(公告)日：2007-03-08

申请号：US11437405

申请日：2006-05-19

申请人： Giancarlo Ragone ,  Luca Crippa ,  Miriam Sangalli ,  Rino Micheloni

发明人： Giancarlo Ragone ,  Luca Crippa ,  Miriam Sangalli ,  Rino Micheloni

IPC分类号： G11C5/14

CPC分类号： H02M3/073 ,  G11C5/145 ,  G11C8/08 ,  G11C16/08 ,  G11C16/12 ,  H02M2003/077 ,  H03K3/356104 ,  H03K17/063 ,  H03K17/6872 ,  H03K17/6874

摘要： A high-voltage switch has a high-voltage input terminal, receiving a high voltage, and an output terminal. A pass transistor, having a control terminal, is connected between the high-voltage input terminal and the output terminal. The output of a voltage-multiplying circuit of the charge-pump type is connected to the control terminal. The voltage-multiplying circuit is of a symmetrical type, has first and second charge-storage means, receiving a clock signal of a periodic type, and has a first circuit branch and a second circuit branch, which are symmetrical to one another and operate in phase opposition with respect to the clock signal.

摘要翻译： 高压开关具有高电压输入端子，接收高电压和输出端子。 具有控制端子的传输晶体管连接在高电压输入端子和输出端子之间。 电荷泵型的倍压电路的输出端与控制端子连接。 电压倍增电路是对称型的，具有第一和第二电荷存储装置，接收周期型的时钟信号，并且具有第一电路支路和第二电路支路，它们彼此对称并在 相对于时钟信号的相位相反。

公开(公告)号：US07184348B2

公开(公告)日：2007-02-27

申请号：US11194739

申请日：2005-08-01

申请人： Luca Crippa ,  Rino Micheloni

发明人： Luca Crippa ,  Rino Micheloni

IPC分类号： G11C7/02

CPC分类号： G11C11/5642 ,  G11C7/12 ,  G11C16/24 ,  G11C16/28

摘要： A sensing circuit is provided for sensing semiconductor memory cells. The sensing circuit includes at least one first circuit branch, a feedback-controlled circuit element in the first circuit branch, a current-to-voltage conversion circuit in the first branch, and at least one comparator. The first circuit branch is coupled to a memory cell to be sensed so as to be run through by a current corresponding to a memory cell state. The feedback-controlled circuit element controls a memory cell access voltage, and the current-to-voltage conversion circuit converts the current into a corresponding converted voltage signal that is indicative of the memory cell state. The comparator compares the converted voltage signal with a comparison voltage for discriminating among at least two different states of the memory cell. The converted voltage signal corresponds to a control signal of the feedback-controlled circuit element. Also provided is a method of sensing a memory cell.

摘要翻译： 提供感测电路用于感测半导体存储单元。 感测电路包括至少一个第一电路支路，第一电路支路中的反馈控制电路元件，第一支路中的电流 - 电压转换电路和至少一个比较器。 第一电路分支耦合到待感测的存储器单元，以便通过对应于存储单元状态的电流运行。 反馈控制电路元件控制存储单元访问电压，并且电流 - 电压转换电路将电流转换成指示存储单元状态的对应的转换电压信号。 比较器将转换的电压信号与比较电压进行比较，以便在存储单元的至少两个不同状态之间进行区分。 转换后的电压信号对应于反馈控制电路元件的控制信号。 还提供了一种感测存储器单元的方法。

公开(公告)号：US07184319B2

公开(公告)日：2007-02-27

申请号：US10675221

申请日：2003-09-30

申请人： Rino Micheloni ,  Giovanni Campardo

发明人： Rino Micheloni ,  Giovanni Campardo

IPC分类号： G11C16/16 ,  G11C16/08 ,  G11C29/04 ,  G11C29/24

CPC分类号： G11C29/82 ,  G11C16/04 ,  G11C16/16 ,  G11C29/44 ,  G11C2029/1208

摘要： The invention relates to a method for erasing non-volatile memory cells, and to a corresponding non-volatile memory device of the programmable and electrically erasable type implementing the method, and comprising a memory cell array organized in a row-and-column layout, and divided in array sectors, including at least one row decode circuit portion being supplied positive and negative voltages. The method is applied whenever the issue of the erase algorithm is negative, and comprises the following steps: forcing an incompletely erased sector into a read condition; scanning the rows of said sector to check for the possible presence of a spurious current indicating a fail state; identifying and electrically isolating the failed row; re-addressing from said failed row to a redundant row provided in the same sector; re-starting the erase algorithm.

摘要翻译： 本发明涉及一种用于擦除非易失性存储单元的方法，以及实现该方法的可编程和电可擦除类型的相应非易失性存储器件，并且包括以行和列布局组织的存储单元阵列， 并且被划分成阵列扇区，包括至少一个行解码电路部分被提供正和负电压。 每当擦除算法的问题为负时，该方法被应用，并且包括以下步骤：强制将未完全擦除的扇区进入读取状态; 扫描所述扇区的行以检查指示故障状态的寄生电流的可能存在; 识别和电隔离失败的行; 从所述故障行重新寻址到在同一扇区中提供的冗余行; 重新启动擦除算法。