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    PACKAGING STRUCTURES AND PACKAGING METHODS FOR ULTRASOUND-ON-CHIP DEVICES
    58.
    发明申请
    PACKAGING STRUCTURES AND PACKAGING METHODS FOR ULTRASOUND-ON-CHIP DEVICES 有权

    公开(公告)号：US20230034707A1

    公开(公告)日：2023-02-02

    申请号：US17962408

    申请日：2022-10-07

    Applicant: BFLY OPERATIONS, INC.

    Inventor： Jianwei Liu ,  Keith G. Fife

    IPC: B81B7/00 ,  B06B1/02 ,  B81C1/00

    Abstract: A method of manufacturing an ultrasound imaging device involves forming an interposer structure, including forming a first metal material within openings through a substate and on top and bottom surfaces of the substrate, patterning the first metal material, forming a dielectric layer over the patterned first metal material, forming openings within the dielectric layer to expose portions of the patterned first metal material, filling the openings with a second metal material, forming a third metal material on the top and bottom surfaces of the substrate, and patterning the third metal material. The method further involves forming a packaging structure for an ultrasound-on-chip device, including attaching a multi-layer flex substrate to a carrier wafer, bonding a first side of an ultrasound-on-chip device to the multi-layer flex substrate, bonding a second side of the ultrasound-on-chip device to a first side of the interposer structure, and removing the carrier wafer.

    Vertical packaging for ultrasound-on-a-chip and related methods
    59.
    发明授权
    Vertical packaging for ultrasound-on-a-chip and related methods 有权

    公开(公告)号：US11426143B2

    公开(公告)日：2022-08-30

    申请号：US17088336

    申请日：2020-11-03

    Applicant: BFLY Operations, Inc.

    Inventor： Keith G. Fife ,  Jianwei Liu

    IPC: H01L29/84 ,  A61B8/00 ,  H01L41/293 ,  H01L41/113

    Abstract: Vertical packaging configurations for ultrasound chips are described. Vertical packaging may involve use of integrated interconnects other than wires for wire bonding. Examples of such integrated interconnects include edge-contact vias, through silicon vias and conductive pillars. Edge-contact vias are vias defined in a trench formed in the ultrasound chip. Multiple vias may be provided for each trench, thus increasing the density of vias. Such vias enable electric access to the ultrasound transducers. Through silicon vias are formed through the silicon handle and provide access from the bottom surface of the ultrasound chip. Conductive pillars, including copper pillars, are disposed around the perimeter of an ultrasound chip and provide access to the ultrasound transducers from the top surface of the chip. Use of these types of packaging techniques can enable a substantial reduction in the dimensions of an ultrasound device.

    Ultrasound apparatuses and methods for fabricating ultrasound devices
    60.
    发明授权
    Ultrasound apparatuses and methods for fabricating ultrasound devices 有权

    公开(公告)号：US11375980B2

    公开(公告)日：2022-07-05

    申请号：US16404672

    申请日：2019-05-06

    Applicant: BFLY Operations, Inc.

    Inventor： Kailiang Chen ,  Nevada J. Sanchez ,  Susan A. Alie ,  Tyler S. Ralston ,  Jonathan M. Rothberg ,  Keith G. Fife ,  Joseph Lutsky

    IPC: H04B1/06 ,  A61B8/08 ,  H04B11/00 ,  A61B8/00

    Abstract: Aspects of the technology described herein relate to an ultrasound device including a first die that includes an ultrasonic transducer, a first application-specific integrated circuit (ASIC) that is bonded to the first die and includes a pulser, and a second ASIC in communication with the second ASIC that includes integrated digital receive circuitry. In some embodiments, the first ASIC may be bonded to the second ASIC and the second ASIC may include analog processing circuitry and an analog-to-digital converter. In such embodiments, the second ASIC may include a through-silicon via (TSV) facilitating communication between the first ASIC and the second ASIC. In some embodiments, SERDES circuitry facilitates communication between the first ASIC and the second ASIC and the first ASIC includes analog processing circuitry and an analog-to-digital converter. In some embodiments, the technology node of the first ASIC is different from the technology node of the second ASIC.

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