公开(公告)号：US5933718A

公开(公告)日：1999-08-03

申请号：US956822

申请日：1997-10-23

申请人： Badih El-Kareh ,  Jack A. Mandelman ,  James G. Ryan

发明人： Badih El-Kareh ,  Jack A. Mandelman ,  James G. Ryan

IPC分类号： H01L27/02 ,  H01L21/8238

CPC分类号： H01L27/0248

摘要： An ESD protective device is formed having a repeatable gap dimension for reliable protection by the formation of a discharge, using the materials of the gate stack for economy and a sacrificial dielectric formed between the plug and the other terminal for repeatable definition of a discharge gap.

摘要翻译： 形成具有可重复的间隙尺寸的ESD保护装置，用于通过用于经济的栅极堆叠的材料和形成在插塞和另一个端子之间的牺牲电介质形成放电来进行可靠的保护，以重复地定义放电间隙。

公开(公告)号：US5198376A

公开(公告)日：1993-03-30

申请号：US909938

申请日：1992-07-07

申请人： Sridhar Divakaruni ,  Badih El-Kareh ,  Eric D. Johnson

发明人： Sridhar Divakaruni ,  Badih El-Kareh ,  Eric D. Johnson

IPC分类号： H01L21/331

CPC分类号： H01L29/6625 ,  Y10S148/096

摘要： A high performance PNP lateral bipolar transistor is described, incorporating at least two trenches extending from the upper P.sup.- surface of a semiconductor substrate almost to a buried N.sup.+ layer. The floor of one trench is heavily N-doped to establish a connection between the buried N.sup.+ layer and an N.sup.- diffusion in the walls of the trench. When the trenches are backfilled with P.sup.+ polysilicon a lateral PNP is formed having a buried base contact.

摘要翻译： 描述了一种高性能PNP横向双极晶体管，其包括从半导体衬底的上P-表面几乎延伸到掩埋的N +层的至少两个沟槽。 一个沟槽的底部被大量N掺杂以在掩埋的N +层和沟槽的壁中的N-扩散之间建立连接。 当沟槽用P +多晶硅回填时，形成具有掩埋基底接触的横向PNP。

公开(公告)号：US4599792A

公开(公告)日：1986-07-15

申请号：US620982

申请日：1984-06-15

申请人： Paul E. Cade ,  Badih El-Kareh ,  Ick W. Kim

发明人： Paul E. Cade ,  Badih El-Kareh ,  Ick W. Kim

IPC分类号： H01L21/02 ,  H01L21/58 ,  H01L21/74 ,  H01L21/762 ,  H01L21/84 ,  H01L23/58 ,  H01L27/00 ,  H01L27/12 ,  H01L21/20 ,  H01L21/31

CPC分类号： H01L24/83 ,  H01L21/74 ,  H01L21/743 ,  H01L21/76251 ,  H01L21/84 ,  H01L23/585 ,  H01L24/26 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  Y10S148/025 ,  Y10S148/05 ,  Y10S148/135

摘要： A method for fabrication of a buried field shield in a semiconductor substrate. A seed substrate is prepared by depositing an epitaxial layer or a seed wafer and then depositing a heavily doped layer and a thin dielectric. The thin dielectric is patterned for contact holes and then a conductive field shield is deposited and patterned. A thick quartz layer is deposited over the field shield and dielectric. A mechanical substrate is anodically bonded to the quartz of the seed substrate and the original seed wafer is etched back to expose the epitaxial layer for further fabrication.

摘要翻译： 一种在半导体衬底中制造掩埋场屏蔽的方法。 通过沉积外延层或种子晶片然后沉积重掺杂层和薄电介质来制备晶种基底。 图案化薄电介质用于接触孔，然后沉积并图案化导电场屏蔽。 在场屏蔽和电介质上沉积厚的石英层。 将机械衬底阳极结合到种子衬底的石英上，并将原始种子晶片回蚀刻以露出外延层以进一步制造。

公开(公告)号：US08654592B2

公开(公告)日：2014-02-18

申请号：US11811702

申请日：2007-06-12

申请人： Badih El-Kareh ,  Leonard Forbes

发明人： Badih El-Kareh ,  Leonard Forbes

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： H01L27/11524 ,  G11C16/0408 ,  G11C16/10 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0642 ,  H01L29/66825 ,  H01L29/7881

摘要： Memory devices and methods of programming and forming the same are disclosed. In one embodiment, a memory device has memory cells contained within dielectric isolation structures to isolate them from at least those memory cells in communication with other bit lines, such as to facilitate forward-bias write operations. The dielectric isolation structures contain an upper well having a first conductivity type and a buried well having a second conductivity type. By forward biasing the junction from the buried well to the upper well, electrons can be injected into charge-storage nodes of memory cells that are contained within the dielectric isolation structures.

摘要翻译： 公开了存储器件及其编程和形成方法。 在一个实施例中，存储器件具有包含在介质隔离结构内的存储器单元，以将它们与至少与其它位线通信的那些存储器单元隔离，以便于正向偏置写入操作。 电介质隔离结构包含具有第一导电类型的上阱和具有第二导电类型的掩埋阱。 通过将接头从掩埋阱向上偏置到上阱，电子可以被注入到包含在介质隔离结构内的存储器单元的电荷存储节点中。

公开(公告)号：US08114753B2

公开(公告)日：2012-02-14

申请号：US12975761

申请日：2010-12-22

申请人： Badih El-Kareh

发明人： Badih El-Kareh

IPC分类号： H01L21/20

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L23/5223 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.

摘要翻译： 提供了一种埋地去耦电容器装置和方法。 根据各种实施例，掩埋去耦电容器装置包括在绝缘体区域上具有掩埋绝缘体区域和顶部半导体区域的绝缘体上半导体衬底。 该装置实施例还包括在绝缘体上半导体衬底中的顶部半导体区域中具有掺杂区域的第一电容器板。 该装置实施例还包括在第一电容器板上的电介质材料和介电材料上的第二电容器板。 根据各种实施例，第一电容器板，电介质材料和第二电容器板形成用于集成电路的去耦电容器。

公开(公告)号：US20110210379A1

公开(公告)日：2011-09-01

申请号：US13086246

申请日：2011-04-13

申请人： Badih El-Kareh ,  Leonard Forbes

发明人： Badih El-Kareh ,  Leonard Forbes

IPC分类号： H01L29/78 ,  H01L29/80

CPC分类号： H01L27/0617 ,  H01L21/8232 ,  H01L21/845 ,  H01L27/085 ,  H01L27/0922 ,  H01L27/098 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7832 ,  H01L29/785 ,  H01L29/8086

摘要： Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate.

摘要翻译： 提供了集成Fin-JFET和Fin-MOSFET的方法，器件和系统。 一个方法实施例包括至少在衬底上形成Fin-MOSFET并且在衬底上至少形成Fin-JFET上形成。

公开(公告)号：US20110092045A1

公开(公告)日：2011-04-21

申请号：US12975761

申请日：2010-12-22

申请人： Badih El-Kareh

发明人： Badih El-Kareh

IPC分类号： H01L21/20

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L23/5223 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.

摘要翻译： 提供了一种埋地去耦电容器装置和方法。 根据各种实施例，掩埋去耦电容器装置包括在绝缘体区域上具有掩埋绝缘体区域和顶部半导体区域的绝缘体上半导体衬底。 该装置实施例还包括在绝缘体上半导体衬底中的顶部半导体区域中具有掺杂区域的第一电容器板。 该装置实施例还包括在第一电容器板上的电介质材料和介电材料上的第二电容器板。 根据各种实施例，第一电容器板，电介质材料和第二电容器板形成用于集成电路的去耦电容器。

公开(公告)号：US07880267B2

公开(公告)日：2011-02-01

申请号：US11510945

申请日：2006-08-28

申请人： Badih El-Kareh

发明人： Badih El-Kareh

IPC分类号： H01L21/02

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L23/5223 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

摘要： A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.

摘要翻译： 提供了一种埋地去耦电容器装置和方法。 根据各种实施例，掩埋去耦电容器装置包括在绝缘体区域上具有掩埋绝缘体区域和顶部半导体区域的绝缘体上半导体衬底。 该装置实施例还包括在绝缘体上半导体衬底中的顶部半导体区域中具有掺杂区域的第一电容器板。 该装置实施例还包括在第一电容器板上的电介质材料和介电材料上的第二电容器板。 根据各种实施例，第一电容器板，电介质材料和第二电容器板形成用于集成电路的去耦电容器。

公开(公告)号：US07670890B2

公开(公告)日：2010-03-02

申请号：US11493229

申请日：2006-07-26

申请人： Badih El-Kareh ,  Hiroshi Yasuda ,  Scott Gerard Balster ,  Philipp Steinmann ,  Joe R. Trogolo

发明人： Badih El-Kareh ,  Hiroshi Yasuda ,  Scott Gerard Balster ,  Philipp Steinmann ,  Joe R. Trogolo

IPC分类号： H01L29/80 ,  H01L21/337

CPC分类号： H01L29/808 ,  H01L29/0642 ,  H01L29/66901

摘要： An junction field effect transistor (JFET) is fashioned with a patterned layer of silicide block (SBLK) material utilized in forming gate, source and drain regions. Utilizing the silicide block in this manner helps to reduce low-frequency (flicker) noise associated with the JFET by suppressing the impact of surface states, among other things.

摘要翻译： 结型场效应晶体管（JFET）用形成栅极，源极和漏极区域的图案化硅化物块（SBLK）材料制成。 以这种方式利用硅化物块有助于通过抑制表面状态的影响来减少与JFET相关的低频（闪烁）噪声。

公开(公告)号：US20100032804A1

公开(公告)日：2010-02-11

申请号：US12537246

申请日：2009-08-06

申请人： Scott Gerard Balster ,  Hiroshi Yasuda ,  Philipp Steinmann ,  Badih El-Kareh

发明人： Scott Gerard Balster ,  Hiroshi Yasuda ,  Philipp Steinmann ,  Badih El-Kareh

IPC分类号： H01L21/331 ,  H01L29/73

CPC分类号： H01L29/7378 ,  H01L21/76283 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/732

摘要： High voltage bipolar transistors built with a BiCMOS process sequence exhibit reduced gain at high current densities due to the Kirk effect. Threshold current density for the onset of the Kirk effect is reduced by the lower doping density required for high voltage operation. The widened base region at high collector current densities due to the Kirk effect extends laterally into a region with a high density of recombination sites, resulting in an increase in base current and drop in the gain. The instant invention provides a bipolar transistor in an IC with an extended unsilicided base extrinsic region in a configuration that does not significantly increase a base-emitter capacitance. Lateral extension of the base extrinsic region may be accomplished using a silicide block layer, or an extended region of the emitter-base dielectric layer. A method of fabricating an IC with the inventive bipolar transistor is also disclosed.

摘要翻译： 由于Kirk效应，用BiCMOS工艺制造的高电压双极型晶体管在高电流密度下表现出减小的增益。 Kirk效应开始的阈值电流密度由于高电压操作所需的较低掺杂密度而降低。 由于Kirk效应，在高集电极电流密度下扩大的基极区域横向扩展到具有高密度复合位点的区域，导致基极电流增加和增益下降。 本发明在IC中提供了具有不显着增加基极 - 发射极电容的构造中的扩展的非硅化基极外部区域的双极晶体管。 可以使用硅化物阻挡层或发射极 - 基极介电层的延伸区域来实现基极外部区域的横向延伸。 还公开了利用本发明的双极晶体管制造IC的方法。