公开(公告)号：US20070224545A1

公开(公告)日：2007-09-27

申请号：US11308393

申请日：2006-03-21

Applicant: Benjamin Szu-Min Lin

Inventor： Benjamin Szu-Min Lin

IPC: G03F7/20

CPC classification number: G03F7/2041 ,  G03F7/70341

Abstract: The invention is directed towards a method for immersion lithography by locally pre-treating the surface of the wafer. The surface of the wafer is treated locally with a pre-treatment process, so that the surface of the wafer is wettable to the later applied immersion liquid. The pre-treatment may includes applying a pre-treating liquid or performing a surface treatment to a predetermined region of the wafer surface or the photoresist layer to enhance the wettability of the surface of the wafer or the photoresist layer. The pre-treatment process is performed concurrently with the step of applying the immersion liquid for exposure.

Abstract translation: 本发明涉及一种通过局部预处理晶片表面的浸没光刻方法。 用预处理工艺局部地处理晶片的表面，使得晶片的表面可润湿到稍后施加的浸没液体。 预处理可以包括对晶片表面或光致抗蚀剂层的预定区域施加预处理液体或进行表面处理以增强晶片或光致抗蚀剂层的表面的润湿性。 预处理过程与施加用于曝光的浸渍液体的步骤同时进行。

公开(公告)号：US20070215040A1

公开(公告)日：2007-09-20

申请号：US11308245

申请日：2006-03-14

Applicant: Yong-Fa Huang ,  Benjamin Szu-Min Lin ,  Chun-Chi Yu ,  Huan-Ting Tseng ,  Bo-Jou Lu

Inventor： Yong-Fa Huang ,  Benjamin Szu-Min Lin ,  Chun-Chi Yu ,  Huan-Ting Tseng ,  Bo-Jou Lu

IPC: B05C13/00

CPC classification number: G03F7/70341 ,  G03F7/70533

Abstract: To avoid the yield of wafers that undergo immersion lithography influencing by delay of post exposure baking (PEB), an operation system adjusts a speed of inputting the wafers to undergo immersion lithography according to a status of wafers that have finished exposure and are waiting for baking. Therefore, the wafers that have finished exposure are transmitted to be baked efficiently and on time.

Abstract translation: 为了避免经历后曝光烘烤（PEB）延迟影响的浸没光刻的晶片的产量，操作系统根据已经完成曝光并正在等待烘焙的晶片的状态来调节输入晶片以进行浸渍光刻的速度 。 因此，已经完成曝光的晶片被传输以有效地并且准时地被烘烤。

公开(公告)号：US20070190805A1

公开(公告)日：2007-08-16

申请号：US11307507

申请日：2006-02-10

Applicant: Benjamin Szu-Min Lin

Inventor： Benjamin Szu-Min Lin

IPC: H01L21/31 ,  H01L21/302 ,  H01L21/76

CPC classification number: H01L21/31144 ,  G03F9/7076 ,  H01L22/34

Abstract: A method of improving the alignment accuracy of the semiconductor devices is described. The method is used for photolithography process, and the photolithography process is aimed at the dielectric layer covered by a hard mask layer, wherein alignment marks are formed under the dielectric layer. The hard mask layer has an absorption index and a thickness, and the product of the absorption index multiplied by the thickness is between 100 and 750. Thereby, the better range of the thickness can be determined to improve the accuracy of alignment.

Abstract translation: 描述了提高半导体器件的对准精度的方法。 该方法用于光刻工艺，并且光刻工艺针对由硬掩模层覆盖的介电层，其中在电介质层下方形成对准标记。 硬掩模层具有吸收指数和厚度，并且吸收指数乘以厚度的乘积在100和750之间。因此，可以确定更好的厚度范围以提高对准精度。

公开(公告)号：US20070020532A1

公开(公告)日：2007-01-25

申请号：US11161084

申请日：2005-07-22

Applicant: Ming-Feng Shieh ,  Benjamin Szu-Min Lin ,  Chun-Chi Yu ,  Jian-Shin Liou

Inventor： Ming-Feng Shieh ,  Benjamin Szu-Min Lin ,  Chun-Chi Yu ,  Jian-Shin Liou

IPC: G03C5/00 ,  G06F17/50 ,  G03F1/00

CPC classification number: G03F1/32 ,  G03F1/36

Abstract: The present invention provides a method for designing a mask. First, a main pattern including at least a strip pattern is formed on the mask substrate. A shift feature is added to one end of the strip pattern of the main pattern. Either the phase shift or the optical transmission or both of the shift feature can be adjusted to optimize the resultant critical dimension between line-ends of the main pattern, thus improving pullback of the line-ends of the strip pattern in the main pattern.

Abstract translation: 本发明提供一种掩模设计方法。 首先，在掩模基板上形成至少包括带状图案的主图案。 移位功能被添加到主图案的条纹图案的一端。 可以调整相移或光学传输或移位特征两者以优化主图案的线端之间的合成临界尺寸，从而改善主图案中带状图案的线端的拉回。

公开(公告)号：US20060133222A1

公开(公告)日：2006-06-22

申请号：US10905265

申请日：2004-12-22

Applicant: Benjamin Szu-Min Lin

Inventor： Benjamin Szu-Min Lin

IPC: G11B21/08

CPC classification number: G03F7/70325

Abstract: A lithography method for improving contrast includes the following steps: To provide a light source. To provide a first plate including at least one opening rotates according to at least one angular velocity. To provide a mask having patterns on it. To provide a second plate including at least one block corresponding to the opening rotates according to the same angular velocity as the first plate. The method also includes a step to perform an exposure process such that zero order light diffracted by the mask is hindered by the block.

Abstract translation: 用于改善对比度的光刻方法包括以下步骤：提供光源。 提供包括至少一个开口的第一板根据至少一个角速度旋转。 提供具有图案的面具。 为了提供一种包括至少一个对应于开口的块的第二板，根据与第一板相同的角速度旋转。 该方法还包括执行曝光处理的步骤，使得由掩模衍射的零级光被块阻挡。

公开(公告)号：US06844143B2

公开(公告)日：2005-01-18

申请号：US10064649

申请日：2002-08-02

Applicant: Benjamin Szu-Min Lin ,  Vencent Chang ,  George Liu ,  Cheng-Chung Chen

Inventor： Benjamin Szu-Min Lin ,  Vencent Chang ,  George Liu ,  Cheng-Chung Chen

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  G03F7/20

CPC classification number: G03F7/0035 ,  H01L21/0271 ,  H01L21/31144 ,  H01L21/76807 ,  Y10S430/151

Abstract: A photolithographic process that involves building a sandwich photoresist structure. A first photoresist layer is formed over a substrate. An anti-reflection layer is formed over the first photoresist layer. A second photoresist layer is formed over the anti-reflection layer. A first photo-exposure is conducted and the exposed second photoresist layer is developed to pattern the second photoresist layer and the anti-reflection layer. Using the second photoresist layer and the anti-reflection layer as a mask, a second photo-exposure and a second photoresist development are conducted to pattern the first photoresist layer.

Abstract translation: 涉及建立夹心光刻胶结构的光刻工艺。 在衬底上形成第一光致抗蚀剂层。 在第一光致抗蚀剂层上形成防反射层。 在防反射层上形成第二光致抗蚀剂层。 进行第一次曝光并且曝光的第二光致抗蚀剂层被显影以对第二光致抗蚀剂层和抗反射层进行图案化。 使用第二光致抗蚀剂层和抗反射层作为掩模，进行第二光曝光和第二光致抗蚀剂显影以对第一光致抗蚀剂层进行图案化。

公开(公告)号：US06511891B2

公开(公告)日：2003-01-28

申请号：US09882747

申请日：2001-06-14

Applicant: Nathna Sun ,  Benjamin Szu-Min Lin ,  Chuan-Fu Wang

Inventor： Nathna Sun ,  Benjamin Szu-Min Lin ,  Chuan-Fu Wang

IPC: H01L2120

CPC classification number: H01L28/60 ,  H01L21/02052 ,  H01L21/32134

Abstract: A method of forming the lower electrode of a capacitor capable of withstanding the flushing force produced by a cleaning agent. A lower electrode having a rectangular profile when viewed from the top is provided. The lower electrode is bounded by a pair of ends and a pair of sides. The ends and the sides are linked together. The ends have a wedge shape. The sides have edges that cave in towards the center, thereby forming a recess region between the sides. A flushing operation is carried out using a cleaning solution. The cleaning solution flows from one end of the electrode to the other end along the sides.

Abstract translation: 一种形成能够承受由清洁剂产生的冲洗力的电容器的下电极的方法。 提供从顶部观察时具有矩形轮廓的下电极。 下电极由一对端部和一对侧面限定。 端部和侧面连接在一起。 端部具有楔形。 这些侧面具有朝向中心凹陷的边缘，从而在两侧之间形成凹陷区域。 使用清洁溶液进行冲洗操作。 清洗液从电极的一端流向另一端。

公开(公告)号：US06277685B1

公开(公告)日：2001-08-21

申请号：US09421261

申请日：1999-10-20

Applicant: Benjamin Szu-Min Lin ,  Jung-Chao Chiou ,  Chin-Hui Lee ,  Chuan-Fu Wang

Inventor： Benjamin Szu-Min Lin ,  Jung-Chao Chiou ,  Chin-Hui Lee ,  Chuan-Fu Wang

IPC: H01L218242

CPC classification number: H01L27/10855 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897

Abstract: The present invention provides a method of forming a node contact hole on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a first dielectric layer positioned on the silicon substrate, two bit lines positioned on the first dielectric layer which form a first groove between the two bit lines and the surface of the first dielectric layer, and a second dielectric layer positioned on each of the two bit lines. A lithographic process is performed to form a photoresist layer on the second dielectric layer with at least one second groove extending down to the second dielectric layer wherein the second groove is positioned above the first groove and is perpendicular to the first groove. An etching process is performed along the second groove of the photoresist layer to remove the second dielectric layer and the first dielectric layer under the second groove down to the surface of the silicon substrate so as to approximately form the node contact hole. Finally, a spacer is formed using an insulating material on the walls of the node contact hole to complete the node contact hole. The spacer completely covers the walls of the two bit lines within the node contact hole but the surface of the silicon substrate exposed at the bottom of the node contact hole is not completely covered by the spacer.

Abstract translation: 本发明提供一种在半导体晶片上形成节点接触孔的方法。 半导体晶片包括硅衬底，位于硅衬底上的第一电介质层，位于第一电介质层上的两个位线，其在两个位线之间形成第一沟槽和第一电介质层的表面;以及第二电介质 层位于两个位线中的每一个上。 执行平版印刷工艺以在第二介电层上形成光致抗蚀剂层，其中至少一个第二凹槽向下延伸到第二介电层，其中第二凹槽位于第一凹槽的上方并且垂直于第一凹槽。 沿着光致抗蚀剂层的第二凹槽进行蚀刻处理，以将第二介电层和第二凹槽下的第一介电层向下移动到硅衬底的表面，以便大致形成节点接触孔。 最后，在节点接触孔的壁上使用绝缘材料形成间隔物，以完成节点接触孔。 间隔件完全覆盖节点接触孔内的两个位线的壁，但是在节点接触孔的底部露出的硅衬底的表面不完全被间隔件覆盖。

公开(公告)号：US6015642A

公开(公告)日：2000-01-18

申请号：US197271

申请日：1998-11-20

Applicant: Benjamin Szu-Min Lin

Inventor： Benjamin Szu-Min Lin

IPC: G03F1/00 ,  G03F9/00

CPC classification number: G03F1/50

Abstract: A fabrication process for a multi-layer photomask. A transparent substrate is provided. An anti-reflecting layer is formed on the substrate. First blinding blocks are formed on the anti-reflecting layer by defining a first blinding layer. A transparent layer is formed along the profile of the structure surface described above. Second blinding blocks are formed on the transparent layer between the first blinding blocks by defining a second blinding layer, wherein a part of the transparent layer on the first blocks is exposed.

Abstract translation: 多层光掩模的制造工艺。 提供透明基板。 在基板上形成防反射层。 通过限定第一致盲层，在抗反射层上形成第一致密块。 沿着上述结构表面的轮廓形成透明层。 通过限定第二堵塞层，在第一堵塞块之间的透明层上形成第二堵塞块，其中露出第一块上的透明层的一部分。

公开(公告)号：US06004845A

公开(公告)日：1999-12-21

申请号：US111306

申请日：1998-07-07

Applicant: Benjamin Szu-Min Lin ,  Der-Yuan Wu

Inventor： Benjamin Szu-Min Lin ,  Der-Yuan Wu

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A method for fabricating crown-shaped a capacitor is provided. The method is comprised of the following steps. First, a dielectric layer is formed on a substrate having a pre-formed field effect transistor, then a contact hole which exposes one of the source/drain regions of the field effect transistor is defined and formed. Then a first conductive layer is formed in the contact hole and on the dielectric layer, a crown-shaped photoresist layer is formed by employing a mask comprising a transmission layer, a partial transmission layer, and a non-transmission layer. Next, the pattern on the photoresist layer is transferred onto the first conductive layer to form a crown-shaped conductive layer. Then, a dielectric film is formed on the top of the crown-shaped conductive layer, and a second conductive layer on the top of the dielectric film.

Abstract translation: 提供一种用于制造冠状电容器的方法。 该方法包括以下步骤。 首先，在具有预形成的场效应晶体管的基板上形成电介质层，然后形成露出场效应晶体管的源/漏区之一的接触孔。 然后在接触孔和电介质层上形成第一导电层，通过采用包括透射层，部分透射层和非透射层的掩模形成冠状光致抗蚀剂层。 接下来，将光致抗蚀剂层上的图案转印到第一导电层上以形成冠状导电层。 然后，在冠状导电层的顶部形成电介质膜，在电介质膜的顶部形成第二导电层。