公开(公告)号：US20130277799A1

公开(公告)日：2013-10-24

申请号：US13451428

申请日：2012-04-19

申请人： Shih-Hung Chen ,  Kuang-Yeu Hsieh

发明人： Shih-Hung Chen ,  Kuang-Yeu Hsieh

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/91

摘要： An example of a capacitor includes a series of ridges and trenches and an interconnect region on the integrated circuit substrate. The series of ridges and trenches and the interconnect region have a capacitor foundation surface with a serpentine cross-sectional shape on the series of ridges and trenches. Electrical conductors are electrically connected to the electrode layers from the interconnect region for access to the electrode layers of the capacitor assembly.

摘要翻译： 电容器的示例包括集成电路基板上的一系列脊和沟槽和互连区域。 一系列脊和沟槽和互连区域具有在一系列脊和沟槽上具有蛇形横截面形状的电容器基座表面。 电导体从互连区域电连接到电极层，用于进入电容器组件的电极层。

公开(公告)号：US20130264719A1

公开(公告)日：2013-10-10

申请号：US13443496

申请日：2012-04-10

申请人： Shih-Hung Chen ,  Kuang-Yeu Hsieh ,  Cheng-Yuan Wang

发明人： Shih-Hung Chen ,  Kuang-Yeu Hsieh ,  Cheng-Yuan Wang

IPC分类号： H01L23/522 ,  H01L21/50

CPC分类号： H01L23/522 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0203 ,  H01L27/1052 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06177 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/73207 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/1431 ,  H01L2924/1435 ,  H01L2924/1443

摘要： A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area.

摘要翻译： 半导体结构包括彼此组装的第一和第二芯片。 第一芯片包括N个第一导线，M个第二导线设置在第一导线上，N个第三导线垂直于第二导线并平行于第一导线，N个第一导通孔连接到第一导电 线，连接到第二导线的M组第二通孔，以及连接到第三导线的N组第三通孔。 第二和第一导电线形成重叠区域。 第三导线和N组第三通孔包括分别设置在重叠区域的第一和第三区域中的至少两个组。 M组第二通孔包括分别设置在重叠区域的第二区域和第四区域中的至少两个组。

公开(公告)号：US20070258284A1

公开(公告)日：2007-11-08

申请号：US11381939

申请日：2006-05-05

申请人： Chiahua Ho ,  Kuang-Yeu Hsieh

发明人： Chiahua Ho ,  Kuang-Yeu Hsieh

IPC分类号： G11C11/14

CPC分类号： G11C11/16 ,  G11C11/1675

摘要： A magnetic memory device comprises a magnetic memory cell that includes a pinned layer and a free layer separated from the pinned layer by an insulating layer. The magnetic memory device also comprises a thermal plate in contact with the free layer. The magnetic memory device can be configured so that a first current flows through the thermal plate heating the thermal plate. The magnetic behavior of the free layer can be altered due to the heating caused by the first current, making it easier to switch the orientation and magnetization of the free layer. A second current can then flow through a bit line near the free layer generating a magnetic field sufficient to switch the orientation of magnetization of the free layer.

摘要翻译： 磁存储器件包括磁存储单元，其包括被钉扎层和通过绝缘层与被钉扎层分离的自由层。 磁存储装置还包括与自由层接触的热板。 磁存储器件可以被配置成使得第一电流流过加热板的加热板。 由于由第一电流引起的加热，自由层的磁性能可以改变，从而更容易切换自由层的取向和磁化。 然后，第二电流可以流过自由层附近的位线，产生足以切换自由层的磁化取向的磁场。

公开(公告)号：US20070091668A1

公开(公告)日：2007-04-26

申请号：US11255606

申请日：2005-10-21

申请人： ChiaHua Ho ,  Kuang-Yeu Hsieh

发明人： ChiaHua Ho ,  Kuang-Yeu Hsieh

IPC分类号： G11C11/00

CPC分类号： G11C11/15 ,  H01L27/228

摘要： A nonvolatile memory device is disclosed. The device includes a substrate, at least one relatively high permeability conductive line, and at least one magnetoresistive memory cell separated from the at least one relatively high permeability conductive line by an insulating material and located in a region of a magnetic field induced in the relatively high permeability conductive line. Methods of making such devices are also disclosed.

摘要翻译： 公开了非易失性存储器件。 该器件包括衬底，至少一个相对高磁导率的导电线路，以及至少一个磁阻存储器单元，其通过绝缘材料与至少一个相对高导磁线路分离，并且位于相对较大导磁线圈中感应的磁场区域中 高导磁线。 还公开了制造这种装置的方法。

公开(公告)号：US08987787B2

公开(公告)日：2015-03-24

申请号：US13443496

申请日：2012-04-10

申请人： Shih-Hung Chen ,  Kuang-Yeu Hsieh ,  Cheng-Yuan Wang

发明人： Shih-Hung Chen ,  Kuang-Yeu Hsieh ,  Cheng-Yuan Wang

IPC分类号： H01L27/118 ,  H01L23/52 ,  H01L23/34 ,  H01L23/48 ,  H01L29/40 ,  H01L21/00 ,  H01L21/336 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L27/105 ,  H01L27/02

CPC分类号： H01L23/522 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0203 ,  H01L27/1052 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06177 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/73207 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/1431 ,  H01L2924/1435 ,  H01L2924/1443

摘要： A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area.

摘要翻译： 半导体结构包括彼此组装的第一和第二芯片。 第一芯片包括N个第一导线，M个第二导线设置在第一导线上，N个第三导线垂直于第二导线并平行于第一导线，N个第一导通孔连接到第一导电 线，连接到第二导线的M组第二通孔，以及连接到第三导线的N组第三通孔。 第二和第一导电线形成重叠区域。 第三导线和N组第三通孔包括分别设置在重叠区域的第一和第三区域中的至少两个组。 M组第二通孔包括分别设置在重叠区域的第二区域和第四区域中的至少两个组。

公开(公告)号：US08072810B2

公开(公告)日：2011-12-06

申请号：US12985743

申请日：2011-01-06

申请人： Tzu-Hsuan Hsu ,  Chao-I Wu ,  Kuang-Yeu Hsieh ,  Ya-Chin King

发明人： Tzu-Hsuan Hsu ,  Chao-I Wu ,  Kuang-Yeu Hsieh ,  Ya-Chin King

IPC分类号： G11C11/34

CPC分类号： G11C16/0466

摘要： The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. the programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure.

摘要翻译： 本发明通过采用用于编程的衬底瞬态热电子技术和用于擦除的衬底瞬时热孔技术来描述电荷俘获存储器的均匀编程方法和均匀擦除方法，其模拟用于NAND存储器操作的FN隧道法。 本发明的方法可应用于包括n沟道或p沟道SONOS类型的存储器和浮动栅（FG）型存储器的各种电荷捕获存储器。 使用衬底瞬态热电子注入进行电荷俘获存储器的编程，其中体偏置电压Vb具有短的脉冲宽度，并且栅极偏置电压Vg具有足以将电子从沟道区域移动到 电荷捕获结构。

公开(公告)号：US07881112B2

公开(公告)日：2011-02-01

申请号：US12538582

申请日：2009-08-10

申请人： Tzu-Hsuan Hsu ,  Chao-I Wu ,  Kuang-Yeu Hsieh ,  Ya-Chin King

发明人： Tzu-Hsuan Hsu ,  Chao-I Wu ,  Kuang-Yeu Hsieh ,  Ya-Chin King

IPC分类号： G11C11/34

CPC分类号： G11C16/0466

摘要： The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. the programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure.

公开(公告)号：US07457149B2

公开(公告)日：2008-11-25

申请号：US11381939

申请日：2006-05-05

申请人： Chiahua Ho ,  Kuang-Yeu Hsieh

发明人： Chiahua Ho ,  Kuang-Yeu Hsieh

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  G11C11/1675

摘要： A magnetic memory device comprises a magnetic memory cell that includes a pinned layer and a free layer separated from the pinned layer by an insulating layer. The magnetic memory device also comprises a thermal plate in contact with the free layer. The magnetic memory device can be configured so that a first current flows through the thermal plate heating the thermal plate. The magnetic behavior of the free layer can be altered due to the heating caused by the first current, making it easier to switch the orientation and magnetization of the free layer. A second current can then flow through a bit line near the free layer generating a magnetic field sufficient to switch the orientation of magnetization of the free layer.

摘要翻译： 磁存储器件包括磁存储器单元，其包括被钉扎层和通过绝缘层与被钉扎层分离的自由层。 磁存储装置还包括与自由层接触的热板。 磁存储器件可以被配置成使得第一电流流过加热板的加热板。 由于由第一电流引起的加热，自由层的磁性能可以改变，从而更容易切换自由层的取向和磁化。 然后，第二电流可以流过自由层附近的位线，产生足以切换自由层的磁化取向的磁场。

公开(公告)号：US07352613B2

公开(公告)日：2008-04-01

申请号：US11255606

申请日：2005-10-21

申请人： ChiaHua Ho ,  Kuang-Yeu Hsieh

发明人： ChiaHua Ho ,  Kuang-Yeu Hsieh

IPC分类号： G11C11/00

CPC分类号： G11C11/15 ,  H01L27/228

摘要： A nonvolatile memory device is disclosed. The device includes a substrate, at least one relatively high permeability conductive line, and at least one magnetoresistive memory cell separated from the at least one relatively high permeability conductive line by an insulating material and located in a region of a magnetic field induced in the relatively high permeability conductive line. Methods of making such devices are also disclosed.

摘要翻译： 公开了非易失性存储器件。 该器件包括衬底，至少一个相对高磁导率的导电线路，以及至少一个磁阻存储器单元，其通过绝缘材料与至少一个相对高导磁线路分离，并且位于相对较大导磁线圈中感应的磁场区域中 高导磁线。 还公开了制造这种装置的方法。

公开(公告)号：US06927136B2

公开(公告)日：2005-08-09

申请号：US10604884

申请日：2003-08-25

申请人： Hsiang-Lan Lung ,  Kuang-Yeu Hsieh ,  Ruichen Liu ,  Tai-Bor Wu ,  Jiun-Yi Tseng

发明人： Hsiang-Lan Lung ,  Kuang-Yeu Hsieh ,  Ruichen Liu ,  Tai-Bor Wu ,  Jiun-Yi Tseng

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L21/336

CPC分类号： B82Y10/00 ,  G11C16/0458 ,  G11C2216/06 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/7887

摘要： A non-volatile memory cell is described. The non-volatile memory cell comprises a substrate, a charge-trapping layer, a gate and a source/drain. The charge-trapping layer comprises an insulating layer and metal nano-particles contained therein, wherein the metal nano-particles are formed with thermal dissociation of an oxide of the same metal. The gate is disposed on the charge-trapping layer, and the source/drain is located in the substrate beside the gate.

摘要翻译： 描述非易失性存储单元。 非易失性存储单元包括衬底，电荷俘获层，栅极和源极/漏极。 电荷捕获层包括绝缘层和其中所含的金属纳米颗粒，其中金属纳米颗粒由相同金属的氧化物的热解离形成。 栅极设置在电荷捕获层上，源极/漏极位于栅极旁边的衬底中。