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    Semiconductor structure and manufacturing method of the same
    3.
    发明授权
    Semiconductor structure and manufacturing method of the same 有权
    半导体结构及其制造方法相同

    公开(公告)号：US08643078B2

    公开(公告)日：2014-02-04

    申请号：US13443417

    申请日：2012-04-10

    申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

    发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh

    IPC分类号： H01L29/788

    CPC分类号： H01L23/3192 ,  H01L27/11565 ,  H01L27/11578 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a base, a stacked structure and a doped layer. The stacked structure is formed on the base, wherein the stacked structure comprises a plurality of conductive strips and a plurality of insulating strips, one of the conductive strips is located between adjacent two insulating strips, the stacked structure has a first side wall, and a long edge of the first side wall is extended along a channel direction. The doped layer is formed in the first side wall, wherein the doped layer is formed by an ion implantation applied to the first side wall, and an acute angle is contained between an implantation direction of the ion implantation and the first side wall.

    摘要翻译： 提供了一种半导体结构及其制造方法。 半导体结构包括基极，层叠结构和掺杂层。 堆叠结构形成在基底上，其中堆叠结构包括多个导电条和多个绝缘条，其中一个导电条位于相邻的两个绝缘条之间，该堆叠结构具有第一侧壁和 第一侧壁的长边缘沿着通道方向延伸。 掺杂层形成在第一侧壁中，其中通过施加到第一侧壁上的离子注入形成掺杂层，并且在离子注入的注入方向和第一侧壁之间包含锐角。

    SELF-ALIGNED STRUCTURE AND METHOD FOR CONFINING A MELTING POINT IN A RESISTOR RANDOM ACCESS MEMORY
    4.
    发明申请
    SELF-ALIGNED STRUCTURE AND METHOD FOR CONFINING A MELTING POINT IN A RESISTOR RANDOM ACCESS MEMORY 有权
    自对准结构和方法，用于在电阻随机访问存储器中配置熔点

    公开(公告)号：US20090020746A1

    公开(公告)日：2009-01-22

    申请号：US12235773

    申请日：2008-09-23

    申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

    发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

    IPC分类号： H01L45/00

    CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

    摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.

    摘要翻译： 制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。 该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料， 选择性材料。 柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。 可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

    Self-Aligned Structure and Method for Confining a Melting Point in a Resistor Random Access Memory
    5.
    发明申请
    Self-Aligned Structure and Method for Confining a Melting Point in a Resistor Random Access Memory 有权
    用于限制电阻随机存取存储器中的熔点的自对准结构和方法

    公开(公告)号：US20080121861A1

    公开(公告)日：2008-05-29

    申请号：US11465094

    申请日：2006-08-16

    申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

    发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

    IPC分类号： H01L45/00

    CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

    摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.

    摘要翻译： 制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。 该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料， 选择性材料。 柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。 可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

    Integrated circuit capacitor and method
    6.
    发明授权
    Integrated circuit capacitor and method 有权
    集成电路电容及方法

    公开(公告)号：US09048341B2

    公开(公告)日：2015-06-02

    申请号：US13451428

    申请日：2012-04-19

    申请人： Shih-Hung Chen ,  Kuang-Yeu Hsieh

    发明人： Shih-Hung Chen ,  Kuang-Yeu Hsieh

    IPC分类号： H01L21/02 ,  H01L49/02

    CPC分类号： H01L28/91

    摘要： An example of a capacitor includes a series of ridges and trenches and an interconnect region on the integrated circuit substrate. The series of ridges and trenches and the interconnect region have a capacitor foundation surface with a serpentine cross-sectional shape on the series of ridges and trenches. Electrical conductors are electrically connected to the electrode layers from the interconnect region for access to the electrode layers of the capacitor assembly.

    摘要翻译： 电容器的示例包括集成电路基板上的一系列脊和沟槽和互连区域。 一系列脊和沟槽和互连区域具有在一系列脊和沟槽上具有蛇形横截面形状的电容器基座表面。 电导体从互连区域电连接到电极层，用于进入电容器组件的电极层。

    Self-aligned structure and method for confining a melting point in a resistor random access memory
    7.
    发明授权
    Self-aligned structure and method for confining a melting point in a resistor random access memory 有权
    用于将熔点限制在电阻随机存取存储器中的自对准结构和方法

    公开(公告)号：US07442603B2

    公开(公告)日：2008-10-28

    申请号：US11465094

    申请日：2006-08-16

    申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

    发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

    IPC分类号： H01L27/13

    CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

    摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.

    摘要翻译： 制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。 该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料， 选择性材料。 柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。 可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

    Memory with off-chip controller
    8.
    发明授权
    Memory with off-chip controller 有权
    具有片外控制器的内存

    公开(公告)号：US09240405B2

    公开(公告)日：2016-01-19

    申请号：US13089652

    申请日：2011-04-19

    申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang Yeu Hsieh

    发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang Yeu Hsieh

    IPC分类号： H01L27/118 ,  H01L27/06 ,  H01L27/02 ,  H01L27/105 ,  H01L27/115

    CPC分类号： H01L27/0688 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578

    摘要： An integrated circuit memory device, including a memory circuit and a peripheral circuit, is described which is suitable for low cost manufacturing. The memory circuit and peripheral circuit for the device are implemented in different layers of a stacked structure. The memory circuit layer and the peripheral circuit layer include complementary interconnect surfaces, which upon mating together establish the electrical interconnection between the memory circuit and the peripheral circuit. The memory circuit layer and the peripheral circuit layer can be formed separately using different processes on different substrates in different fabrication lines. This enables the use of independent fabrication process technologies, one arranged for the memory array, and another arranged for the supporting peripheral circuit. The separate circuitry can then be stacked and bonded together.

    摘要翻译： 描述了包括存储器电路和外围电路的集成电路存储器件，其适用于低成本制造。 用于器件的存储器电路和外围电路被实现在堆叠结构的不同层中。 存储器电路层和外围电路层包括互补的互连表面，其在配合时一起建立存储器电路和外围电路之间的电互连。 存储电路层和外围电路层可以在不同的制造线路中的不同基板上使用不同的工艺分别形成。 这使得能够使用独立的制造工艺技术，一种被布置用于存储器阵列，另一种被布置用于支持外围电路。 然后可以将单独的电路堆叠并结合在一起。

    Memory with Off-Chip Controller
    9.
    发明申请
    Memory with Off-Chip Controller 有权
    具有片外控制器的存储器

    公开(公告)号：US20120267689A1

    公开(公告)日：2012-10-25

    申请号：US13089652

    申请日：2011-04-19

    申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang Yeu Hsieh

    发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang Yeu Hsieh

    IPC分类号： H01L27/10 ,  H01L21/82

    CPC分类号： H01L27/0688 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578

    摘要： An integrated circuit memory device, including a memory circuit and a peripheral circuit, is described which is suitable for low cost manufacturing. The memory circuit and peripheral circuit for the device are implemented in different layers of a stacked structure. The memory circuit layer and the peripheral circuit layer include complementary interconnect surfaces, which upon mating together establish the electrical interconnection between the memory circuit and the peripheral circuit. The memory circuit layer and the peripheral circuit layer can be formed separately using different processes on different substrates in different fabrication lines. This enables the use of independent fabrication process technologies, one arranged for the memory array, and another arranged for the supporting peripheral circuit. The separate circuitry can then be stacked and bonded together.

    摘要翻译： 描述了包括存储器电路和外围电路的集成电路存储器件，其适用于低成本制造。 用于器件的存储器电路和外围电路被实现在堆叠结构的不同层中。 存储器电路层和外围电路层包括互补的互连表面，其在配合时一起建立存储器电路和外围电路之间的电互连。 存储电路层和外围电路层可以在不同的制造线路中的不同基板上使用不同的工艺分别形成。 这使得能够使用独立的制造工艺技术，一种被布置用于存储器阵列，另一种被布置用于支持外围电路。 然后可以将单独的电路堆叠并结合在一起。

    Semiconductor structure with improved capacitance of bit line
    10.
    发明授权
    Semiconductor structure with improved capacitance of bit line 有权
    具有改善位线电容的半导体结构

    公开(公告)号：US08704205B2

    公开(公告)日：2014-04-22

    申请号：US13594353

    申请日：2012-08-24

    申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

    发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

    IPC分类号： H01L47/00

    CPC分类号： H01L27/11582 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575

    摘要： A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.

    摘要翻译： 具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。 第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。 导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。 第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。 第一组晶体管结构在第一体积区域周围具有第一栅极。 第一导线连接到第一栅极以控制施加到第一栅极的电压。