公开(公告)号：US06638391B1

公开(公告)日：2003-10-28

申请号：US10177306

申请日：2002-06-19

申请人： Chia-Lin Hsu ,  Art Yu ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

发明人： Chia-Lin Hsu ,  Art Yu ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

IPC分类号： H01L21302

CPC分类号： B24B37/30

摘要： A wafer carrier assembly for a chemical mechanical polishing apparatus and a polishing method using the same are provided. The present wafer carrier assembly comprises a first plate, a second plate and a flexible membrane. The first plate has a plurality of protrusions formed on a bottom surface thereof and the second plate has a plurality of apertures passing through. Each of the protrusions is matched with one of the apertures to enable the first plate and the second plate to detachably combine together. The flexible membrane is positioned under the second plate and contacts it. A surface of the flexible membrane opposite to the surface of the flexible membrane contacting the second plate provides a wafer-receiving surface.

摘要翻译： 提供了一种用于化学机械抛光装置的晶片载体组件和使用其的抛光方法。 本晶片载体组件包括第一板，第二板和柔性膜。 第一板具有在其底表面上形成的多个突起，并且第二板具有穿过的多个孔。 每个突起与其中一个孔匹配，以使得第一板和第二板能够可拆卸地组合在一起。 柔性膜定位在第二板下方并与其接触。 与柔性膜的与第二板接触的表面相对的柔性膜的表面提供了晶片接收表面。

公开(公告)号：US09559189B2

公开(公告)日：2017-01-31

申请号：US13447286

申请日：2012-04-16

申请人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chia-Lin Hsu

发明人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chia-Lin Hsu

IPC分类号： H01L29/76 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L29/7853 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795

摘要： The present invention provides a non-planar FET which includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.

摘要翻译： 本发明提供一种非平面FET，其包括衬底，鳍结构，栅极和栅极电介质层。 翅片结构设置在基板上。 翅片结构包括与基底相邻的第一部分，其中第一部分朝向基底的一侧收缩。 门设置在翅片结构上。 栅介质层设置在鳍结构和栅极之间。 本发明还提供了一种制造非平面FET的方法。

公开(公告)号：US20140065775A1

公开(公告)日：2014-03-06

申请号：US13603425

申请日：2012-09-05

申请人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu

发明人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu

IPC分类号： H01L21/336

CPC分类号： H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： A method of fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, which includes at least a fin structure and at least a gate semiconductor layer disposed thereon. The gate semiconductor layer covers a portion of the fin structure. Then a sacrificial layer is deposited to cover the fin structure entirely. Subsequently, a top surface of the fin structure is exposed from the sacrificial layer through an etching process. A material layer is then deposited, which covers the gate semiconductor layer, the fin structure and the sacrificial layer conformally. Finally, the material layer is etched until the top surface of the fin structure is exposed and a first spacer is concurrently formed on side surfaces of the gate semiconductor layer.

摘要翻译： 制造半导体器件的方法包括以下步骤。 首先，提供至少包括翅片结构和至少设置在其上的栅极半导体层的半导体衬底。 栅极半导体层覆盖翅片结构的一部分。 然后沉积牺牲层以完全覆盖翅片结构。 随后，翅片结构的顶表面通过蚀刻工艺从牺牲层露出。 然后沉积材料层，其共形地覆盖栅极半导体层，鳍结构和牺牲层。 最后，蚀刻材料层直到翅片结构的顶表面露出，并且在栅极半导体层的侧表面上同时形成第一间隔物。

公开(公告)号：US08440511B1

公开(公告)日：2013-05-14

申请号：US13298264

申请日：2011-11-16

申请人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Min-Ying Hsu ,  Hsin-Huei Wu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

发明人： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Min-Ying Hsu ,  Hsin-Huei Wu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

IPC分类号： H01L21/00

CPC分类号： H01L21/306 ,  H01L29/66795 ,  H01L29/7854

摘要： A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer and a patterned hard mask sequentially formed thereon, removing the patterned hard mask, performing a thermal treatment to rounding the patterned semiconductor layer with a process temperature lower than 800° C., and sequentially forming a gate dielectric layer and a gate layer covering a portion of the patterned semiconductor layer on the semiconductor substrate.

摘要翻译： 一种用于制造多栅极晶体管器件的方法包括：提供具有图案化半导体层的半导体衬底和在其上依次形成的图案化硬掩模，去除图案化的硬掩模，进行热处理以使处理温度低于 800℃，并顺序地形成覆盖半导体衬底上的图案化半导体层的一部分的栅极电介质层和栅极层。

公开(公告)号：US08314031B2

公开(公告)日：2012-11-20

申请号：US12726347

申请日：2010-03-18

申请人： Chia-Lin Hsu

发明人： Chia-Lin Hsu

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/3212

摘要： A planarization process for a pre-damascene structure is described, wherein the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask. A first CMP step is conducted using a first slurry to remove the second material layer outside the damascene opening. A second CMP step is conducted using a second slurry to remove the metal hard mask.

摘要翻译： 描述了一种预镶嵌结构的平面化方法，其中预镶嵌结构包括设置在其中具有镶嵌开口的第一材料层上的金属硬掩模和填充镶嵌开口并覆盖金属的第二材料层 硬面膜 使用第一浆料进行第一CMP步骤以除去镶嵌开口外部的第二材料层。 使用第二浆料进行第二CMP步骤以除去金属硬掩模。

公开(公告)号：US20070032077A1

公开(公告)日：2007-02-08

申请号：US11161530

申请日：2005-08-08

申请人： Tzung-Yu Hung ,  Chien-Chung Huang ,  Chao-Ching Hsieh ,  Chia-Lin Hsu

发明人： Tzung-Yu Hung ,  Chien-Chung Huang ,  Chao-Ching Hsieh ,  Chia-Lin Hsu

IPC分类号： H01L21/44

CPC分类号： H01L21/76828 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76883

摘要： A method for manufacturing a metal plug is described. A substrate with an opening is provided. Then, a barrier layer is formed on a surface of the opening. Thereafter, a metallic layer is formed over the substrate so that the opening is also filled. Next, a planarization process is performed to remove the metallic layer outside the opening. One main feature of the present invention is the performance of at least a high temperature treatment after the metallic layer is formed. Due to the high temperature treatment, internal stress between different layers is released.

摘要翻译： 对金属插头的制造方法进行说明。 提供具有开口的基板。 然后，在开口的表面上形成阻挡层。 此后，在基板上形成金属层，使得开口也被填充。 接下来，进行平面化处理以去除开口外部的金属层。 本发明的一个主要特征是在形成金属层之后进行至少高温处理。 由于高温处理，不同层之间的内部应力被释放。

公开(公告)号：US20060211242A1

公开(公告)日：2006-09-21

申请号：US11308341

申请日：2006-03-17

申请人： Chia-Lin Hsu ,  Chih-Chan Yu ,  Chien-Chung Huang

发明人： Chia-Lin Hsu ,  Chih-Chan Yu ,  Chien-Chung Huang

IPC分类号： H01L21/44

CPC分类号： H01L21/31053 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76883

摘要： A method of forming a plug is provided. First, a substrate comprising at least a dielectric layer is provided, and a patterned hard mask is formed on the dielectric layer to define a position of at least a plug hole. Subsequently, the dielectric layer is etched for forming the plug hole. A barrier layer and a conductive layer are formed on the substrate, and the plug hole is filled by the conductive layer. Thereafter, first, second, and third chemical mechanical polishing processes are performed in turn. Finally, a fourth chemical mechanical polishing process is performed to remove portions of the conductive layer.

摘要翻译： 提供一种形成插头的方法。 首先，提供包括至少介电层的基板，并且在电介质层上形成图案化的硬掩模，以限定至少一个插塞孔的位置。 随后，蚀刻电介质层以形成插塞孔。 在基板上形成阻挡层和导电层，并且通过导电层填充插塞孔。 此后，依次执行第一，第二和第三化学机械抛光工艺。 最后，执行第四种化学机械抛光工艺以去除部分导电层。

公开(公告)号：US06797190B2

公开(公告)日：2004-09-28

申请号：US10383983

申请日：2003-03-06

申请人： Chia-Lin Hsu ,  Art Yu ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

发明人： Chia-Lin Hsu ,  Art Yu ,  Shih-Hsun Hsu ,  Hsueh-Chung Chen

IPC分类号： B24D1100

CPC分类号： B24B37/30

摘要： A wafer carrier assembly for a chemical mechanical polishing apparatus and a polishing method using the same are provided. The present wafer carrier assembly comprises a first plate, a second plate and a flexible membrane. The first plate has a plurality of protrusions formed on a bottom surface thereof and the second plate has a plurality of apertures passing through. Each of the protrusions is matched with one of the apertures to enable the first plate and the second plate to detachably combine together. The flexible membrane is positioned under the second plate and contacts it. A surface of the flexible membrane opposite to the surface of the flexible membrane contacting the second plate provides a wafer-receiving surface.

摘要翻译： 提供了一种用于化学机械抛光装置的晶片载体组件和使用其的抛光方法。 本晶片载体组件包括第一板，第二板和柔性膜。 第一板具有在其底表面上形成的多个突起，并且第二板具有穿过的多个孔。 每个突起与其中一个孔匹配，以使得第一板和第二板能够可拆卸地组合在一起。 柔性膜定位在第二板下方并与其接触。 与柔性膜的与第二板接触的表面相对的柔性膜的表面提供了晶片接收表面。