公开(公告)号：US09318567B2

公开(公告)日：2016-04-19

申请号：US13603425

申请日：2012-09-05

申请人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu

发明人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu

IPC分类号： H01L21/31 ,  H01L21/84 ,  H01L21/311 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： A method of fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, which includes at least a fin structure and at least a gate semiconductor layer disposed thereon. The gate semiconductor layer covers a portion of the fin structure. Then a sacrificial layer is deposited to cover the fin structure entirely. Subsequently, a top surface of the fin structure is exposed from the sacrificial layer through an etching process. A material layer is then deposited, which covers the gate semiconductor layer, the fin structure and the sacrificial layer conformally. Finally, the material layer is etched until the top surface of the fin structure is exposed and a first spacer is concurrently formed on side surfaces of the gate semiconductor layer.

摘要翻译： 制造半导体器件的方法包括以下步骤。 首先，提供至少包括翅片结构和至少设置在其上的栅极半导体层的半导体衬底。 栅极半导体层覆盖翅片结构的一部分。 然后沉积牺牲层以完全覆盖翅片结构。 随后，翅片结构的顶表面通过蚀刻工艺从牺牲层露出。 然后沉积材料层，其共形地覆盖栅极半导体层，鳍结构和牺牲层。 最后，蚀刻材料层直到翅片结构的顶表面露出，并且在栅极半导体层的侧表面上同时形成第一间隔物。

公开(公告)号：US20130270612A1

公开(公告)日：2013-10-17

申请号：US13447286

申请日：2012-04-16

申请人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chia-Lin Hsu

发明人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chia-Lin Hsu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7853 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795

摘要： The present invention provides a non-planar FET which includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.

摘要翻译： 本发明提供一种非平面FET，其包括衬底，鳍结构，栅极和栅极电介质层。 翅片结构设置在基板上。 翅片结构包括与基底相邻的第一部分，其中第一部分朝向基底的一侧收缩。 门设置在翅片结构上。 栅介质层设置在鳍结构和栅极之间。 本发明还提供一种制造非平面FET的方法。

公开(公告)号：US09559189B2

公开(公告)日：2017-01-31

申请号：US13447286

申请日：2012-04-16

申请人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chia-Lin Hsu

发明人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chia-Lin Hsu

IPC分类号： H01L29/76 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L29/7853 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795

摘要： The present invention provides a non-planar FET which includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.

摘要翻译： 本发明提供一种非平面FET，其包括衬底，鳍结构，栅极和栅极电介质层。 翅片结构设置在基板上。 翅片结构包括与基底相邻的第一部分，其中第一部分朝向基底的一侧收缩。 门设置在翅片结构上。 栅介质层设置在鳍结构和栅极之间。 本发明还提供了一种制造非平面FET的方法。

公开(公告)号：US20140065775A1

公开(公告)日：2014-03-06

申请号：US13603425

申请日：2012-09-05

申请人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu

发明人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Chia-Lin Hsu

IPC分类号： H01L21/336

CPC分类号： H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： A method of fabricating a semiconductor device includes the following steps. First, a semiconductor substrate is provided, which includes at least a fin structure and at least a gate semiconductor layer disposed thereon. The gate semiconductor layer covers a portion of the fin structure. Then a sacrificial layer is deposited to cover the fin structure entirely. Subsequently, a top surface of the fin structure is exposed from the sacrificial layer through an etching process. A material layer is then deposited, which covers the gate semiconductor layer, the fin structure and the sacrificial layer conformally. Finally, the material layer is etched until the top surface of the fin structure is exposed and a first spacer is concurrently formed on side surfaces of the gate semiconductor layer.

摘要翻译： 制造半导体器件的方法包括以下步骤。 首先，提供至少包括翅片结构和至少设置在其上的栅极半导体层的半导体衬底。 栅极半导体层覆盖翅片结构的一部分。 然后沉积牺牲层以完全覆盖翅片结构。 随后，翅片结构的顶表面通过蚀刻工艺从牺牲层露出。 然后沉积材料层，其共形地覆盖栅极半导体层，鳍结构和牺牲层。 最后，蚀刻材料层直到翅片结构的顶表面露出，并且在栅极半导体层的侧表面上同时形成第一间隔物。

公开(公告)号：US08551829B2

公开(公告)日：2013-10-08

申请号：US12943015

申请日：2010-11-10

申请人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

发明人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/70

CPC分类号： H01L29/66795

摘要： A method for manufacturing a multi-gate transistor device includes providing a semiconductor substrate having a first patterned semiconductor layer formed thereon, sequentially forming a gate dielectric layer and a gate layer covering a portion of the first patterned semiconductor layer on the semiconductor substrate, removing a portion of the first patterned semiconductor layer to form a second patterned semiconductor layer, and performing a selective epitaxial growth process to form an epitaxial layer on a surface of the second patterned semiconductor layer.

摘要翻译： 一种制造多栅极晶体管器件的方法包括：提供其上形成有第一图案化半导体层的半导体衬底，顺序地形成栅极电介质层和覆盖半导体衬底上的第一图案化半导体层的一部分的栅极层， 以形成第二图案化半导体层，并且执行选择性外延生长工艺以在第二图案化半导体层的表面上形成外延层。

公开(公告)号：US20130193585A1

公开(公告)日：2013-08-01

申请号：US13363390

申请日：2012-02-01

申请人： Chin-Fu Lin ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chin-Cheng Chien

发明人： Chin-Fu Lin ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chin-Cheng Chien

IPC分类号： H01L23/48 ,  H01L21/302

CPC分类号： H01L21/3085 ,  H01L21/3086 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a through silicon via (TSV) structure, in which, a patterned mask is formed on a substrate, the patterned mask has an opening, a spacer-shaped structure is formed on a sidewall of the opening, and a via hole having a relatively enlarged opening is formed by etching the spacer-shaped structure and the substrate through the opening after the spacer-shaped structure is formed. A TSV structure, in which, a via hole has an opening portion and a body portion, the opening portion is a relatively enlarged opening and has a tapered shape having an opening size of an upper portion greater than an opening size of a lower portion.

公开(公告)号：US20130078780A1

公开(公告)日：2013-03-28

申请号：US13241188

申请日：2011-09-22

申请人： Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chin-Cheng Chien ,  Chun-Yuan Wu

发明人： Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chin-Cheng Chien ,  Chun-Yuan Wu

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/28229 ,  H01L29/517 ,  H01L29/78

摘要： A semiconductor process includes the following steps. An interlayer is formed on a substrate. A first metallic oxide layer is formed on the interlayer. A reduction process is performed to reduce the first metallic oxide layer into a metal layer. A high temperature process is performed to transform the metal layer to a second metallic oxide layer.

摘要翻译： 半导体工艺包括以下步骤。 在基板上形成中间层。 在中间层上形成第一金属氧化物层。 进行还原处理以将第一金属氧化物层还原成金属层。 执行高温处理以将金属层转变为第二金属氧化物层。

公开(公告)号：US08822284B2

公开(公告)日：2014-09-02

申请号：US13370231

申请日：2012-02-09

申请人： Chin-Fu Lin ,  Chin-Cheng Chien ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Chih-Chien Liu

发明人： Chin-Fu Lin ,  Chin-Cheng Chien ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Chih-Chien Liu

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/318 ,  H01L21/314

CPC分类号： H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/3141 ,  H01L21/3185 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L27/10879 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795

摘要： A method for fabricating FinFETs is described. A semiconductor substrate is patterned to form odd fins. Spacers are formed on the substrate and on the sidewalls of the odd fins, wherein each spacer has a substantially vertical sidewall. Even fins are then formed on the substrate between the spacers. A semiconductor structure for forming FinFETs is also described, which is fabricated using the above method.

摘要翻译： 描述了制造FinFET的方法。 图案化半导体衬底以形成奇数鳍片。 间隔件形成在基底上和奇数翅片的侧壁上，其中每个间隔件具有基本垂直的侧壁。 然后在间隔件之间的基板上均匀形成翅片。 还描述了用于形成FinFET的半导体结构，其使用上述方法制造。

公开(公告)号：US08647941B2

公开(公告)日：2014-02-11

申请号：US13211319

申请日：2011-08-17

申请人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

发明人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

IPC分类号： H01L21/8238

CPC分类号： H01L29/7846 ,  H01L21/76283 ,  H01L29/1054 ,  H01L29/66651 ,  H01L29/78

摘要： A method of forming a semiconductor device includes the following steps. A semiconductor substrate having a first strained silicon layer is provided. Then, an insulating region such as a shallow trench isolation (STI) is formed, where a depth of the insulating region is substantially larger than a depth of the first strained silicon layer. Subsequently, the first strained silicon layer is removed, and a second strained silicon layer is formed to substitute the first strained silicon layer.

摘要翻译： 形成半导体器件的方法包括以下步骤。 提供具有第一应变硅层的半导体衬底。 然后，形成诸如浅沟槽隔离（STI）的绝缘区域，其中绝缘区域的深度基本上大于第一应变硅层的深度。 随后，去除第一应变硅层，形成第二应变硅层以代替第一应变硅层。

公开(公告)号：US08497198B2

公开(公告)日：2013-07-30

申请号：US13243485

申请日：2011-09-23

申请人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

发明人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

IPC分类号： H01L21/4763 ,  H01L21/3205 ,  H01L21/336

CPC分类号： H01L29/66795

摘要： A semiconductor process is described as follows. A plurality of dummy patterns is formed on a substrate. A mask material layer is conformally formed on the substrate, so as to cover the dummy patterns. The mask material layer has an etching rate different from that of the dummy patterns. A portion of the mask material layer is removed, so as to form a mask layer on respective sidewalls of each dummy pattern. An upper surface of the mask layer and an upper surface of each dummy pattern are substantially coplanar. The dummy patterns are removed. A portion of the substrate is removed using the mask layer as a mask, so as to form a plurality of fin structures and a plurality of trenches alternately arranged in the substrate. The mask layer is removed.

摘要翻译： 半导体工艺描述如下。 在基板上形成多个虚设图案。 在基板上共形形成掩模材料层，以覆盖虚设图案。 掩模材料层具有与虚拟图案不同的蚀刻速率。 除去掩模材料层的一部分，以便在每个虚设图案的各个侧壁上形成掩模层。 掩模层的上表面和每个虚拟图案的上表面基本上共面。 虚拟图案被去除。 使用掩模层作为掩模去除衬底的一部分，以便形成多个翅片结构和交替布置在衬底中的多个沟槽。 去除掩模层。