公开(公告)号：US20130334575A1

公开(公告)日：2013-12-19

申请号：US13527259

申请日：2012-06-19

Applicant: Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

IPC: H01L27/10 ,  H01L21/768

CPC classification number: H01L27/11578 ,  H01L27/11565

Abstract: The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked nonvolatile memory structures. Word line trenches are made in the partly oxidized lines, by removing the unoxidized lines from the intermediate parts of the partly oxidized lines, leaving the plurality of oxidized lines at the outer parts of the plurality of partly oxidized lines. Word lines are made in the word line trenches over the plurality of stacked nonvolatile memory structures.

Abstract translation: 该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。 在多个堆叠的非易失性存储器结构上制造部分氧化的材料线如硅。 通过从部分氧化的线的中间部分去除未氧化的线，在多个部分氧化的线的外部部分留下多条氧化线，在部分氧化的线中形成字线沟槽。 在多个堆叠的非易失性存储器结构中的字线沟槽中形成字线。

公开(公告)号：US20130214340A1

公开(公告)日：2013-08-22

申请号：US13401634

申请日：2012-02-21

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

IPC: H01L29/68 ,  H01L21/283

CPC classification number: H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/7881 ,  H01L29/792

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, and a first conductive layer. The first stacked structure is formed on the substrate and includes a conductive structure and an insulating structure, and the conductive structure is disposed adjacent to the insulating structure. The first conductive layer is formed on the substrate and surrounds two side walls and a part of the top portion of the first stacked structure for exposing a portion of the first stacked structure.

Abstract translation: 提供了一种半导体结构及其制造方法。 半导体结构包括基板，第一堆叠结构和第一导电层。 第一堆叠结构形成在基板上，并且包括导电结构和绝缘结构，并且导电结构邻近于绝缘结构设置。 第一导电层形成在基板上并且包围第一层叠结构的两个侧壁和顶部的一部分，用于暴露第一堆叠结构的一部分。

公开(公告)号：US08503213B2

公开(公告)日：2013-08-06

申请号：US13078311

申请日：2011-04-01

Applicant: Shih-Hung Chen ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Hang-Ting Lue

IPC: G11C5/06

CPC classification number: H01L27/11578 ,  G11C13/0002 ,  G11C16/0483 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/11573

Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit lines at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of word lines, which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor strips on the stacks and the word lines.

Abstract translation: 3D存储器件包括多个由绝缘材料隔开的导电材料条带形式的脊形叠层，排列成可通过解码电路耦合到读出放大器的位线。 二极管与字符串的公共源选择端的字符串选择连接到位线。 导电材料条具有在脊形叠层的侧面上的侧表面。 可以耦合到行解码器的多个字线在多个脊形叠层上正交延伸。 存储元件位于堆叠上的半导体条的侧表面和字线之间的交叉点处的界面区域的多层阵列中。

公开(公告)号：US08432719B2

公开(公告)日：2013-04-30

申请号：US13008384

申请日：2011-01-18

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: G11C11/00

CPC classification number: H01L27/11556 ,  G11C8/16 ,  G11C16/0416 ,  H01L27/11524

Abstract: A 3D stacked AND-type flash memory structure comprises several horizontal planes of memory cells arranged in a three-dimensional array, and each horizontal plane comprising several word lines and several of charge trapping multilayers arranged alternately, and the adjacent word lines spaced apart from each other with each charge trapping multilayer interposed between; a plurality of sets of bit lines and source lines arranged alternately and disposed vertically to the horizontal planes; and a plurality of sets of channels and sets of insulation pillars arranged alternatively, and disposed perpendicularly to the horizontal planes, wherein one set of channels is sandwiched between the adjacent sets of bit lines and source lines.

Abstract translation: 3D堆叠的AND型闪速存储器结构包括以三维阵列布置的多个存储单元的水平面，并且每个水平面包括交替布置的多个字线和几个电荷俘获多层，并且相邻的字线与每个 其他每个电荷捕获多层介于其间; 交替布置并垂直于水平面布置的多组位线和源极线; 以及交替布置并且垂直于水平面布置的多组绝缘柱和一组绝缘柱，其中一组通道夹在相邻的位线组和源极线之间。

公开(公告)号：US08426294B2

公开(公告)日：2013-04-23

申请号：US13476964

申请日：2012-05-21

Applicant: Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Hang-Ting Lue

Inventor： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee ,  Hang-Ting Lue

IPC: H01L29/76

CPC classification number: G11C16/0458 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/11578 ,  H01L27/11582

Abstract: A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

Abstract translation: 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。 半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。 半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。 电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。 该设备可以作为3D和解码的闪存操作。

公开(公告)号：US08315095B2

公开(公告)日：2012-11-20

申请号：US13310546

申请日：2011-12-02

Applicant: Hang-Ting Lue ,  Szu-Yu Wang

Inventor： Hang-Ting Lue ,  Szu-Yu Wang

IPC: G11C11/34

CPC classification number: H01L29/792 ,  G11C16/0483 ,  G11C16/0491 ,  H01L21/265 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833

Abstract: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.

公开(公告)号：US20120182806A1

公开(公告)日：2012-07-19

申请号：US13078311

申请日：2011-04-01

Applicant: Shih-Hung Chen ,  Hang-Ting Lue

Inventor： Shih-Hung Chen ,  Hang-Ting Lue

IPC: G11C16/04

CPC classification number: H01L27/11578 ,  G11C13/0002 ,  G11C16/0483 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/11573

Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit lines at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of word lines, which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor strips on the stacks and the word lines.

Abstract translation: 3D存储器件包括多个由绝缘材料隔开的导电材料条带形式的脊形叠层，排列成可通过解码电路耦合到读出放大器的位线。 二极管与字符串的公共源选择端的字符串选择连接到位线。 导电材料条具有在脊形叠层的侧面上的侧表面。 可以耦合到行解码器的多个字线在多个脊形叠层上正交延伸。 存储元件位于堆叠上的半导体条的侧表面和字线之间的交叉点处的界面区域的多层阵列中。

公开(公告)号：US20120181654A1

公开(公告)日：2012-07-19

申请号：US13223116

申请日：2011-08-31

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: H01L21/3105 ,  H01L29/06

CPC classification number: H01L21/3105 ,  H01L21/8221 ,  H01L27/11578

Abstract: Technology is described herein for manufacturing a three-dimensional 3D stacked memory structure having multiple layers of single crystal silicon or other semiconductor. The multiple layers of single crystal semiconductor are suitable for implementing multiple levels of high performance memory cells.

Abstract translation: 本文描述了用于制造具有多层单晶硅或其他半导体的三维3D堆叠存储器结构的技术。 多层单晶半导体适用于实现多级高性能存储单元。

公开(公告)号：US20120168841A1

公开(公告)日：2012-07-05

申请号：US12981121

申请日：2010-12-29

Applicant: Shih Hung Chen ,  Hang-Ting Lue

Inventor： Shih Hung Chen ,  Hang-Ting Lue

IPC: H01L29/788 ,  G03F7/20

CPC classification number: H01L27/11565 ,  G03F7/0035 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/1157 ,  H01L27/11573

Abstract: An integrated circuit memory comprises a set of lines each line having parallel X direction line portions in a first region and Y direction line portions in a second region. The second region is offset from the first region. The lengths of the X direction line portions are substantially longer than the lengths of the Y direction line portions. The X direction and Y direction line portions have respective first and second pitches with the second pitch being at least 3 times larger than the first pitch. Contact pickup areas are at the Y direction line portions. In some examples, the lines comprise word lines or bit lines. The memory can be created using multiple patterning methods to create lines of material and then the parallel X direction line portions and parallel Y direction line portions.

Abstract translation: 集成电路存储器包括一组线，每条线在第一区域中具有平行的X方向线部分，在第二区域具有Y方向线部分。 第二区域偏离第一区域。 X方向线部分的长度比Y方向线部分的长度大得多。 X方向和Y方向线部分具有相应的第一和第二间距，其中第二间距比第一间距大至少3倍。 触点拾取区域在Y方向线部分。 在一些示例中，这些线包括字线或位线。 可以使用多个图案化方法来创建记忆，以产生材料线，然后平行的X方向线部分和平行的Y方向线部分。

公开(公告)号：US08183617B2

公开(公告)日：2012-05-22

申请号：US12430817

申请日：2009-04-27

Applicant: Yi-Hsuan Hsiao ,  Erh-Kun Lai ,  Hang-Ting Lue

Inventor： Yi-Hsuan Hsiao ,  Erh-Kun Lai ,  Hang-Ting Lue

IPC: H01L29/76

CPC classification number: H01L29/665 ,  G11C16/0408 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes.

Abstract translation: 描述了具有肖特基源和漏极的非易失性存储单元的注入方法。 载流子注入效率由硅化物和硅的界面特性控制。 通过控制栅极和源极/漏极的重叠以及通过控制注入，激活和/或栅极过程来修改肖特基势垒。