公开(公告)号：US07236008B1

公开(公告)日：2007-06-26

申请号：US11611122

申请日：2006-12-14

申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  Andy L. Lee ,  David Lewis

发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  Andy L. Lee ,  David Lewis

IPC分类号： G06F7/38 ,  H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/17728

摘要： Circuits, methods, and apparatus that provide integrated circuits having memories with multiple sizes. The memories may be dedicated embedded memories, or they may be distributed memories formed using memories or lookup tables in logic elements or other appropriate circuits. Configuration bits not needed by logic elements used for distributed memories can be used for data storage as well. These various memories may be combined or otherwise linked or chained together in different combinations to form larger memories of varying sizes.

摘要翻译： 提供具有多种尺寸的存储器的集成电路的电路，方法和装置。 存储器可以是专用的嵌入式存储器，或者它们可以是使用逻辑元件或其他适当电路中的存储器或查找表形成的分布式存储器。 用于分布式存储器的逻辑元件不需要的配置位也可以用于数据存储。 这些各种存储器可以以不同的组合组合或以其他方式链接或链接在一起以形成不同大小的较大存储器。

公开(公告)号：US06351152B1

公开(公告)日：2002-02-26

申请号：US09401743

申请日：1999-09-23

申请人： Srinivas T. Reddy ,  Anil Gupta

发明人： Srinivas T. Reddy ,  Anil Gupta

IPC分类号： H03K1762

CPC分类号： H03K17/693 ,  H03K17/005

摘要： A look-up table circuit implemented with MOS transistors that uses combinational logic to generate signals that enable the transistors. A circuit using 16 inputs and 4 select lines is disclosed. Two of the select lines are used as inputs to combinational logic including four NOR gates to generate enable signals for transistors in a third stage of the circuit. This produces a reduction in the propagation delay of a signal from the input to the output of the look-up table circuit.

摘要翻译： 用MOS晶体管实现的查找表电路，其使用组合逻辑来产生使晶体管能够实现的信号。 公开了使用16个输入和4个选择线的电路。 选择线中的两条被用作组合逻辑的输入，包括四个或非门以产生电路第三级晶体管的使能信号。 这导致信号从输入到查找表电路的输出的传播延迟的减小。

公开(公告)号：US6107820A

公开(公告)日：2000-08-22

申请号：US82081

申请日：1998-05-20

申请人： David E. Jefferson ,  Srinivas T. Reddy

发明人： David E. Jefferson ,  Srinivas T. Reddy

IPC分类号： H03K19/173 ,  G06F11/20 ,  G06F7/38

CPC分类号： H03K19/17764 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1778

摘要： Redundant circuitry is provided for a programmable logic device that uses an interleaved input multiplexer circuit arrangement. The programmable logic device has at least one row of logic regions and has multiple columns, each of which contains one of the interleaved input multiplexers and one of the logic regions. A set of conductors associated with the row of logic regions is used to convey signals between the logic regions. Each interleaved logic region distributes logic signals from the conductors in the row to two adjacent logic regions. Bypass circuitry is provided in each column for bypassing the interleaved input multiplexer and logic region in that column. If a defect is detected in a column during testing of the device, the manufacturer can repair the device using the bypass circuitry to bypass that column. Spare logic is provided to replace the circuitry lost when a defective column is bypassed.

公开(公告)号：US6037829A

公开(公告)日：2000-03-14

申请号：US591121

申请日：1996-01-25

申请人： Srinivas T. Reddy ,  Anil Gupta

发明人： Srinivas T. Reddy ,  Anil Gupta

IPC分类号： H03K17/00 ,  H03K17/693 ,  H03K17/62 ,  G11C8/00

CPC分类号： H03K17/693 ,  H03K17/005

摘要： A look-up table circuit implemented with MOS transistors that uses combinational logic to generate signals that enable the transistors. A circuit using 16 inputs and 4 select lines is disclosed. Two of the select lines are used as inputs to combinational logic including four NOR gates to generate enable signals for transistors in a third stage of the circuit. This produces a reduction in the propagation delay of a signal from the input to the output of the look-up table circuit.

公开(公告)号：US06344755B1

公开(公告)日：2002-02-05

申请号：US09691424

申请日：2000-10-18

申请人： Srinivas T. Reddy ,  Manuel Mejia ,  Andy L. Lee ,  Bruce B. Pedersen

发明人： Srinivas T. Reddy ,  Manuel Mejia ,  Andy L. Lee ,  Bruce B. Pedersen

IPC分类号： H03K19003

CPC分类号： H03K19/17764 ,  H03K19/17736

摘要： A programmable logic device is provided that allows a redundant row of programmable logic to be shifted into place to repair the device when a defect is detected in a row of programmable logic on the device. The redundant row is shifted into place by routing programming data into the normal logic and the redundant logic while bypassing the row of logic containing the defect. Switching circuitry may be used to direct programming data into the serial inputs of various data registers that are then used to load the programming data into the device. The patterns of programmable connections that are made between programmable logic regions on the device and vertical and horizontal conductors also allow redundant logic to be shifted into place. Some connections between the logic and the horizontal and vertical conductors may be identical within a column to facilitate shifting. Other connections may only partially overlap between respective rows. The partially overlapping pattern allows the connections to be less regular, which increases flexibility when routing signals on the device.

摘要翻译： 提供了一种可编程逻辑器件，其允许在器件上的可编程逻辑行中检测到缺陷时将冗余的可编程逻辑行移位到位以修复器件。 通过将编程数据路由到正常逻辑和冗余逻辑中来绕过包含缺陷的逻辑行，将冗余行移位到位。 开关电路可用于将编程数据引导到各种数据寄存器的串行输入，然后将其用于将编程数据加载到器件中。 在设备上的可编程逻辑区域和垂直和水平导体之间进行的可编程连接的模式也允许将冗余逻辑移位到位。 逻辑和水平和垂直导体之间的一些连接可以在列内相同以便于移动。 其他连接可能仅在相应行之间部分重叠。 部分重叠的模式允许连接不太规则，这在设备上路由信号时增加灵活性。

公开(公告)号：US06337578B2

公开(公告)日：2002-01-08

申请号：US09795870

申请日：2001-02-28

申请人： David E. Jefferson ,  Srinivas T. Reddy

发明人： David E. Jefferson ,  Srinivas T. Reddy

IPC分类号： H03K19173

CPC分类号： H03K19/17764 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1778

摘要： Redundant circuitry is provided for a programmable logic device that uses an interleaved input multiplexer circuit arrangement. The programmable logic device has at least one row of logic regions and has multiple columns, each of which contains one of the interleaved input multiplexers and one of the logic regions. A set of conductors associated with the row of logic regions is used to convey signals between the logic regions. Each interleaved logic region distributes logic signals from the conductors in the row to two adjacent logic regions. Bypass circuitry is provided in each column for bypassing the interleaved input multiplexer and logic region in that column. If a defect is detected in a column during testing of the device, the manufacturer can repair the device using the bypass circuitry to bypass that column. Spare logic is provided to replace the circuitry lost when a defective column is bypassed.

摘要翻译： 为可编程逻辑器件提供冗余电路，该可编程逻辑器件使用交错输入多路复用器电路装置。 可编程逻辑器件具有至少一行逻辑区域，并且具有多个列，每个列包含交错输入多路复用器之一和逻辑区中的一个。 与逻辑区域行相关联的一组导体用于在逻辑区域之间传送信号。 每个交错逻辑区域将逻辑信号从行中的导体分配到两个相邻的逻辑区域。 在每列中提供旁路电路，以绕过该列中的交错输入多路复用器和逻辑区域。 如果在测试设备期间在列中检测到缺陷，制造商可以使用旁路电路修复设备以绕过该列。 提供备用逻辑来替代绕过故障列时丢失的电路。

公开(公告)号：US06191608B1

公开(公告)日：2001-02-20

申请号：US08851250

申请日：1997-05-05

申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  Kerry Veenstra ,  Andreas Papaliolios ,  Chiakang Sung ,  Richard Shaw Terrill ,  Rina Raman ,  Robert Richard Noel Bielby

发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  Kerry Veenstra ,  Andreas Papaliolios ,  Chiakang Sung ,  Richard Shaw Terrill ,  Rina Raman ,  Robert Richard Noel Bielby

IPC分类号： H03K19177

CPC分类号： H03K19/17776 ,  G06F17/5054 ,  H03K19/1774 ,  H03K19/17748

摘要： Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

摘要翻译： 可编程逻辑阵列器件由网络中的编程设备编程，这些器件可以利用任何大小或复杂度的程序来编程任何数量的这种逻辑器件。 编程数据和控制的源可以是微处理器或一个或多个串行EPROM，一个EPROM配备有时钟电路。 可以使用几个并行数据流来加速编程操作。 可以提供具有可编程可变速度的时钟电路以便于具有不同速度特性的编程逻辑器件。 编程协议可以包括在每个编程数据传输之后从逻辑设备到编程数据源的确认，使得源可以以逻辑设备能够接受该数据的速度自动发送编程数据。

公开(公告)号：US5986470A

公开(公告)日：1999-11-16

申请号：US970830

申请日：1997-11-14

申请人： Richard G. Cliff ,  Srinivas T. Reddy ,  Rina Raman ,  L. Todd Cope ,  Joseph Huang ,  Bruce B. Pedersen

发明人： Richard G. Cliff ,  Srinivas T. Reddy ,  Rina Raman ,  L. Todd Cope ,  Joseph Huang ,  Bruce B. Pedersen

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/1736 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764

摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.

摘要翻译： 可编程逻辑阵列集成电路器件包括以有意义的行和列的二维阵列布置在器件上的多个可编程逻辑区域。 互连导体与每行和列相关联。 与每行相关联的互连导体包括沿着整个行的连续延伸的一些连接导体，一些连续导体仅沿着该行的左半部或右半部连续延伸。 为了增加逻辑区域可以连接到行和列导体的灵活性，相邻区域成对，并且提供电路以允许每对的输出被交换以驱动行和列导体。 逻辑区域中的寄存器仍然可以用于其他目的，不用于注册逻辑区域的主要组合输出。 还提供了许多其他增强功能。

公开(公告)号：US5764080A

公开(公告)日：1998-06-09

申请号：US519045

申请日：1995-08-24

申请人： Joseph Huang ,  Richard G. Cliff ,  Srinivas T. Reddy

发明人： Joseph Huang ,  Richard G. Cliff ,  Srinivas T. Reddy

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17744

摘要： In a programmable logic array integrated circuit device, various techniques are used to increase the flexibility with which the core logic of the device can be connected to the input and/or output pins of the device. While the techniques shown greatly increase circuit flexibility, they avoid the unnecessary overhead of interconnectivity which is completely general.

公开(公告)号：US5694058A

公开(公告)日：1997-12-02

申请号：US619072

申请日：1996-03-20

申请人： Srinivas T. Reddy ,  Chiakang Sung ,  Bonnie I-Keh Wang

发明人： Srinivas T. Reddy ,  Chiakang Sung ,  Bonnie I-Keh Wang

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17796

摘要： In order to increase routing flexibility for the output signals of logic modules in programmable logic array integrated circuit devices, the output signal of each logic module can be swapped with the output signal of another logic module by a first level of signal swapping circuitry. The output signals of the first level of swapping circuitry can be further swapped with output signals of other first level swapping circuits by a second level of signal swapping circuitry to provide still more routing flexibility for the logic module output signals.

摘要翻译： 为了增加可编程逻辑阵列集成电路器件中的逻辑模块的输出信号的布线灵活性，每个逻辑模块的输出信号可以通过第一级信号交换电路与另一个逻辑模块的输出信号进行交换。 第一级交换电路的输出信号可以通过第二级信号交换电路进一步与其它第一级交换电路的输出信号交换，以为逻辑模块输出信号提供更多的路由灵活性。