公开(公告)号：US06532185B2

公开(公告)日：2003-03-11

申请号：US09792605

申请日：2001-02-23

申请人： Jean Louis Calvignac ,  Peter Irma August Barri ,  Ivan Oscar Clemminck ,  Kent Harold Haselhorst ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Bart Joseph Gerard Pauwels ,  Fabrice Jean Verplanken ,  Miroslav Vrana

发明人： Jean Louis Calvignac ,  Peter Irma August Barri ,  Ivan Oscar Clemminck ,  Kent Harold Haselhorst ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Bart Joseph Gerard Pauwels ,  Fabrice Jean Verplanken ,  Miroslav Vrana

IPC分类号： G11C800

CPC分类号： H04L49/901 ,  G06F12/0607 ,  H04L49/90 ,  H04L49/9031

摘要： Network processors commonly utilize DRAM chips for the storage of data. Each DRAM chip contains multiple banks for quick storage of data and access to that data. Latency in the transfer or the ‘write’ of data into memory can occur because of a phenomenon referred to as memory bank polarization. By a procedure called quadword rotation, this latency effect is effectively eliminated. Data frames received by the network processor are transferred to a receive queue (FIFO). The frames are divided into segments that are written into the memory of the DRAM in accordance with a formula that rotates the distribution of each segment into the memory banks of the DRAM.

公开(公告)号：US07506081B2

公开(公告)日：2009-03-17

申请号：US10850219

申请日：2004-05-20

申请人： Peter Irma August Barri ,  Jean Louis Calvignac ,  Kent Harold Haselhorst ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken ,  Miroslav Vrana

发明人： Peter Irma August Barri ,  Jean Louis Calvignac ,  Kent Harold Haselhorst ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken ,  Miroslav Vrana

IPC分类号： G06F3/00

CPC分类号： G11C7/1066 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/4093

摘要： A Network Processor includes a Fat Pipe Port and a memory sub-system that provides sufficient data to satisfy the Bandwidth requirements of the Fat Pipe Port. The memory sub-system includes a plurality of DDR DRAMs controlled so that data is extracted from one DDR DRAM or simultaneously from a plurality of the DDR DRAMs. By controlling the DDR DRAMs so that the outputs provide data serially or in parallel, the data Bandwidth is adjustable over a wide range. Similarly, data is written serially into one DDR DRAM or simultaneously into multiple DDR DRAMs. As a consequence buffers with data from the same frame are written into or read from different DDR DRAMs.

摘要翻译： 网络处理器包括胖管端口和存储器子系统，其提供足够的数据以满足胖管端口的带宽要求。 存储器子系统包括被控制的多个DDR DRAM，从而从一个DDR DRAM提取数据或者同时从多个DDR DRAM中提取数据。 通过控制DDR DRAM，使得输出串行或并行提供数据，数据带宽可在宽范围内调节。 类似地，数据被串行地写入一个DDR DRAM或同时被写入多个DDR DRAM。 因此，来自相同帧的数据的缓冲器被写入或从不同的DDR DRAM中读取。

公开(公告)号：US07383244B2

公开(公告)日：2008-06-03

申请号：US11045634

申请日：2005-01-28

申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC分类号： G06F7/00

CPC分类号： G06F17/30985 ,  H04L45/7457 ,  Y10S707/99931 ,  Y10S707/99933 ,  Y10S707/99936 ,  Y10S707/99942 ,  Y10S707/99943 ,  Y10S707/99945

摘要： Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first: match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.

摘要翻译： 当搜索具有可变长度模式或前缀的表时，用于查找最长前缀的新型数据结构，方法和装置匹配搜索。 要找到完全匹配或最佳匹配前缀，模式必须一次比较一下，直到找到完全匹配或第一个匹配。 这需要“n”个比较或存储器访问来识别最接近的匹配模式。 树的建立方式使得匹配结果保证是最佳匹配，无论是完全匹配还是最长匹配前缀。 使用所有鸟的踪迹和相关的前缀长度可以确定路线中正确的前缀结果。 通过构建，搜索树在步道或树的步行期间在第一次比较之前或之后提供最佳的匹配前缀。

公开(公告)号：US07130916B2

公开(公告)日：2006-10-31

申请号：US09791336

申请日：2001-02-23

申请人： Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

发明人： Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC分类号： G06F15/167 ,  G06F12/00 ,  G06F12/16 ,  G06F13/28 ,  G06F9/44 ,  H04L12/54 ,  G06F15/16 ,  G06F12/14 ,  G06F13/00 ,  G06F3/00 ,  G06F9/46

CPC分类号： H04L49/3081 ,  G06F13/4243 ,  H04L2012/5681

摘要： A method and system for reducing memory accesses by inserting qualifiers in control blocks. In one embodiment, a system comprises a processor configured to process frames of data. The processor may comprise a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each control block, e.g., frame control block, buffer control block, may comprise one or more qualifier fields that comprise information unrelated to the current control block. Instead, qualifiers may comprise information related to an another control block. The last frame control block in a queue as well as the last buffer control block associated with a frame control block may comprise fields with no information thereby reducing memory accesses to access information in those fields.

公开(公告)号：US06952424B1

公开(公告)日：2005-10-04

申请号：US09548912

申请日：2000-04-13

申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC分类号： H04L12/28 ,  H04L12/56 ,  H04L29/06

CPC分类号： H04L49/90

摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a weighted fair queueing system where the position of the next service in a best efforts system for using bandwidth which is not used by committed bandwidth is determined based on the length of the frame and the weight of the particular flow. A “back pressure” system keeps a flow from being selected if its output cannot accept an additional frame because the current level of that port queue exceeds a threshold.

摘要翻译： 一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。 本发明包括一种方法和系统，用于根据存储的与信息单元的各种源相关联的优先级来调度来自网络处理单元的处理的信息单元（或帧）的出口。 优选实施例中的优先级包括低延迟服务，最小带宽，加权公平排队以及用于在较长时间内防止用户继续超过其服务水平的系统。 本发明包括一个加权公平排队系统，其中基于帧的长度和特定流的权重确定用于使用未被承诺带宽使用的带宽的最佳努力系统中的下一个服务的位置。 如果该端口队列的当前级别超过阈值，则“背压”系统的输出不能接受额外的帧，从而保持流量的选择。

公开(公告)号：US06947931B1

公开(公告)日：2005-09-20

申请号：US09544992

申请日：2000-04-06

申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC分类号： G06F17/30 ,  G06F17/00

CPC分类号： G06F17/30985 ,  H04L45/7457 ,  Y10S707/99931 ,  Y10S707/99933 ,  Y10S707/99936 ,  Y10S707/99942 ,  Y10S707/99943 ,  Y10S707/99945

摘要： Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.

摘要翻译： 当搜索具有可变长度模式或前缀的表时，用于查找最长前缀的新型数据结构，方法和装置匹配搜索。 要找到完全匹配或最匹配的前缀，模式必须一次比较一下，直到发现确切或第一个匹配。 这需要“n”个比较或存储器访问来识别最接近的匹配模式。 树的建立方式使得匹配结果保证是最佳匹配，无论是完全匹配还是最长匹配前缀。 使用所有鸟的踪迹和相关的前缀长度可以确定路线中正确的前缀结果。 通过构建，搜索树在步道或树的步行期间在第一次比较之前或之后提供最佳的匹配前缀。

公开(公告)号：US06868082B1

公开(公告)日：2005-03-15

申请号：US09385603

申请日：1999-08-30

申请人： James Johnson Allen, Jr. ,  Brian Mitchell Bass ,  Jean Louis Calvignac ,  Santosh Prasad Gaur ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

发明人： James Johnson Allen, Jr. ,  Brian Mitchell Bass ,  Jean Louis Calvignac ,  Santosh Prasad Gaur ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC分类号： G06F13/28 ,  G06F13/40 ,  H04L12/28

CPC分类号： G06F13/4022

摘要： A network apparatus comprising storage units storing configuration information about the network apparatus, an input network interface to at least one network physical line, at least one processor receiving network data from said network interface, processing said data, storing information about said network data in said storage units, storing said data as formatted data units in said storage units, a first bus interface to two bus connections, a first hardware component reading said configuration information and said information about data stored in said storing units and steering said formatted data units stored in said storage units to at least one of the two bus connections of said first bus interface, a second bus interface to two bus connections, an output network interface to at least one network physical line, a second hardware component reading formatted data units arriving on at least one of the two bus connections of said second bus interface and storing said formatted data units in said storage units, said at least one processor reading said formatted data units from said storage units, processing them and sending them as network data to at least one network physical line through said output network interface. On the basis of this network processor, it is possible to build switching systems by adding one network processor and at least one switch; it is also possible to build double density blades attached to two redundant switch fabrics which can also be accessed concurrently.

摘要翻译： 一种网络装置，包括存储关于网络装置的配置信息的存储单元，至少一个网络物理线路的输入网络接口，至少一个处理器，从所述网络接口接收网络数据，处理所述数据，将关于所述网络数据的信息存储在所述 存储单元，将所述数据作为格式化数据单元存储在所述存储单元中，到两个总线连接的第一总线接口，读取所述配置信息的第一硬件组件和关于存储在所述存储单元中的数据的所述信息，以及控制所存储的所述格式化数据单元 所述存储单元到所述第一总线接口的两个总线连接中的至少一个，到两个总线连接的第二总线接口，到至少一个网络物理线的输出网络接口，第二硬件组件读取到达 所述第二总线接口的两个总线连接中的至少一个，并存储所述格式化的数据 所述至少一个处理器从所述存储单元读取所述格式化的数据单元，处理它们并通过所述输出网络接口将它们作为网络数据发送到至少一个网络物理线路。 在该网络处理器的基础上，可以通过添加一个网络处理器和至少一个交换机构建交换系统; 也可以构建连接到两个冗余交换结构的双密度刀片，这两个冗余交换机也可以同时访问。

公开(公告)号：US06842443B2

公开(公告)日：2005-01-11

申请号：US10002932

申请日：2001-10-23

申请人： James Johnson Allen, Jr. ,  Brian Mitchell Bass ,  Jean Louis Calvignac ,  Santosh Prasad Gaur ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

发明人： James Johnson Allen, Jr. ,  Brian Mitchell Bass ,  Jean Louis Calvignac ,  Santosh Prasad Gaur ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC分类号： G06F15/16 ,  G06F15/177 ,  H04L12/56 ,  H04Q3/00 ,  H04Q3/545 ,  H04L12/28 ,  H04B7/216

CPC分类号： H04Q3/002 ,  H04L45/742 ,  H04L49/254 ,  H04L49/351 ,  H04L49/354 ,  H04L49/602 ,  H04L2212/00 ,  H04Q3/5455 ,  H04Q2213/1302 ,  H04Q2213/13034 ,  H04Q2213/1304 ,  H04Q2213/13103 ,  H04Q2213/13104 ,  H04Q2213/13106 ,  H04Q2213/13107 ,  H04Q2213/13322

摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

摘要翻译： 一种网络交换设备，用于这种设备的部件，以及操作这样一种设备的方法，其中通过多个接口处理器和形成在半导体衬底上的一组外围元件之间的协作来增强数据流处理和灵活性。 接口处理器和外围设备一起形成一个网络处理器，能够在执行指导网络中的数据流的指令的情况下与包括可选的交换结构设备在内的其他元件进行协作。

公开(公告)号：US06804249B1

公开(公告)日：2004-10-12

申请号：US09548911

申请日：2000-04-13

申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC分类号： H04L1256

CPC分类号： H04L47/28 ,  H04L45/02 ,  H04L47/2441 ,  H04L47/50 ,  H04L2012/5681

摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to service based on minimum bandwidth specifications where position in the queue is adjusted after each service based on minimum bandwidth specificaiton and the length of frame, a process which is subject to rounding errors. To avoid the accumulation of rounding errors inequitably influencing the position of some in the queue, a system to adjust for the rounding errors adds an increased measure of fairness to the system.

摘要翻译： 一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。 本发明包括一种方法和系统，用于基于最小带宽规范来调度来自网络处理单元的处理的信息单元（或帧）的处理的信息单元（或帧），其中基于最小带宽规定在每个服务之后调整队列中的位置，并且 帧的长度，一个进行舍入误差的过程。 为了避免累积误差不均衡地影响队列中某些队员的位置，调整舍入误差的系统增加了系统的公平性。

公开(公告)号：US06769033B1

公开(公告)日：2004-07-27

申请号：US09384691

申请日：1999-08-27

申请人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Piyush Chunilal Patel ,  Mark Anthony Rinaldi ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

发明人： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Ross Boyd Leavens ,  Piyush Chunilal Patel ,  Mark Anthony Rinaldi ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC分类号： G06F900

CPC分类号： H04L49/602 ,  G06F15/80 ,  H04L49/351

摘要： A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of an embedded processor complex with a suite of peripherals, all formed on a common semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate, while storage of transiting data flow portions is provided by memory peripherals and interfaces to external memory elements.

摘要翻译： 可用于网络交换设备的网络处理器和操作这样的处理器的方法，其中通过嵌入式处理器复合体与一组外围设备的协作来增强数据流处理和灵活性，这些外围设备都形成在公共半导体衬底上。 接口处理器提供用于入站和出站数据流的数据路径，并且在存储在形成于半导体衬底上的指令存储器中的指令的控制下操作，同时由存储器外围设备和与外部存储器元件的接口提供过渡数据流部分的存储。