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78 条记录 (耗时 0.03 秒)

    Digital delay line with low insertion delay
    51.
    发明授权
    Digital delay line with low insertion delay 失效
    具有低插入延迟的数字延迟线

    公开(公告)号：US06285229B1

    公开(公告)日：2001-09-04

    申请号：US09471898

    申请日：1999-12-23

    申请人： Albert M. Chu ,  Frank D. Ferraiolo ,  John A. Fifield ,  Teresa Thi Nguyen ,  Michael Sofranko

    发明人： Albert M. Chu ,  Frank D. Ferraiolo ,  John A. Fifield ,  Teresa Thi Nguyen ,  Michael Sofranko

    IPC分类号： H03H1126

    CPC分类号： H03K5/131 ,  H03K5/133 ,  H03K2005/00058

    摘要： A variable digital delay line with an insertion delay as low as a single delay element yet capable of providing a large programmable delay with a small simple control mechanism. A loop connects an input to an output through selectable first delay elements such as 2:1 muxes and selectable second delay elements such as pairs of inverters by way of a plurality of intermediate nodes having a tap. A plurality of sneak paths are available wherein the loop by passes a remainder of first delay elements and/or second delay elements by way of the taps at the intermediate nodes.

    摘要翻译： 一种可变数字延迟线，其插入延迟低至单个延迟元件，但能够利用小的简单控制机制提供大的可编程延迟。 环路通过可选择的第一延迟元件（例如2：1多路复用器）和可选择的第二延迟元件（例如成对的反相器）通过具有抽头的多个中间节点将输入连接到输出。 多个潜行路径是可用的，其中循环通过中间节点处的抽头通过第一延迟元件的剩余部分和/或第二延迟元件。

    Self-timed circuit having critical path timing detection
    52.
    发明授权
    Self-timed circuit having critical path timing detection 失效
    具有关键路径定时检测的自定时电路

    公开(公告)号：US5870404A

    公开(公告)日：1999-02-09

    申请号：US694120

    申请日：1996-08-08

    申请人： Frank D. Ferraiolo ,  John E. Gersbach ,  Charles J. Masenas, Jr. ,  Norman J. Rohrer ,  Bruce W. Singer

    发明人： Frank D. Ferraiolo ,  John E. Gersbach ,  Charles J. Masenas, Jr. ,  Norman J. Rohrer ,  Bruce W. Singer

    IPC分类号： G06F1/08 ,  G06K5/04 ,  G11B5/00

    CPC分类号： G06F1/08

    摘要： A self-timed circuit for use a clocked logic system is disclosed that comprises a timing detection device for detecting a timing margin of a critical path, the critical path being a path that limits the speed of the system. The circuit further comprises increase logic for increasing the speed of the system clock if the timing margin allows it, and decrease logic for decreasing the speed of the system clock if the timing margin indicates such a need. The increase and decrease logic comprise threshold generator and reset logic, and clock control logic.

    摘要翻译： 公开了一种用于使用时钟逻辑系统的自定时电路，其包括用于检测关键路径的定时裕度的定时检测装置，该关键路径是限制系统速度的路径。 该电路还包括用于增加系统时钟的速度的增加逻辑，如果定时裕度允许的话，并且如果定时裕度表示这样的需要，则降低用于降低系统时钟速度的逻辑。 增加和减少逻辑包括阈值发生器和复位逻辑以及时钟控制逻辑。

    Anti-latching mechanism for phase lock loops
    53.
    发明授权
    Anti-latching mechanism for phase lock loops 失效
    锁相环锁止机构

    公开(公告)号：US5694087A

    公开(公告)日：1997-12-02

    申请号：US592902

    申请日：1996-01-29

    申请人： Frank D. Ferraiolo ,  John E. Gersbach ,  Masayuki Hayashi ,  Ilya I. Novof ,  Charles J. Masenas, Jr.

    发明人： Frank D. Ferraiolo ,  John E. Gersbach ,  Masayuki Hayashi ,  Ilya I. Novof ,  Charles J. Masenas, Jr.

    IPC分类号： H03L7/10 ,  H03L7/093

    CPC分类号： H03L7/10

    摘要： A protective circuit for a phase lock loop ensures that the VCO does not initiate a runaway condition when outputting a signal having a frequency higher than the feedback divider can respond to. During normal phase lock operation, a counter keeps track of the PLL input signal and is reset by the feedback divider. In the runaway condition the counter is not reset and triggers a control signal to the VCO. A second counter can be used to keep track of the feedback divider output and to reset the first counter. When the first counter far outruns the second counter the control signal is triggered.

    摘要翻译： 用于锁相环的保护电路确保当输出具有高于反馈分配器的频率的信号可以响应时，VCO不会发起失控状况。 在正常锁相操作期间，计数器跟踪PLL输入信号，并由反馈分频器复位。 在失控状态下，计数器不复位，并触发VCO的控制信号。 第二个计数器可用于跟踪反馈分频器输出并复位第一个计数器。 当第一个计数器远远超出第二个计数器时，触发控制信号。

    Edge detector
    54.
    发明授权
    Edge detector 失效
    边缘检测器

    公开(公告)号：US5577078A

    公开(公告)日：1996-11-19

    申请号：US452446

    申请日：1995-05-26

    申请人： Richard C. Jordan ,  Robert S. Capowski ,  Daniel F. Casper ,  Frank D. Ferraiolo ,  William C. Laviola ,  Peter R. Tomaszewski

    发明人： Richard C. Jordan ,  Robert S. Capowski ,  Daniel F. Casper ,  Frank D. Ferraiolo ,  William C. Laviola ,  Peter R. Tomaszewski

    IPC分类号： H03L7/06 ,  H04L7/033 ,  H04L7/04 ,  H04L7/00

    CPC分类号： H04L7/0338

    摘要： An edge detector has a digital phase locking loop in which one of the signals (e.g., the data signal) is coupled to a delay chain that develops a series of incrementally phase delayed versions of the input. Adjacent phase delayed pairs are selected, one pair at a time, and are compared to the other signal (e.g., the clock signal) to determine if an edge of the clock falls between the edges of the data signal in the selected phase pair, or falls outside the edges of the selected phase pair, on one side or the other thereof. If the clock edge falls outside the selected pair, a control signal selects another pair for comparison and the process is repeated until, for example, the data edges are aligned with the positive going edge of the clock. With a clock frequency equal to twice data frequency, the data can then be sampled on the falling edge of the clock.

    摘要翻译： 边缘检测器具有数字锁相环，其中信号之一（例如，数据信号）耦合到产生输入的一系列增量相位延迟版本的延迟链。 选择相邻相位延迟对，每次一对，并与另一个信号（例如，时钟信号）进行比较，以确定时钟的边沿是否落在所选相位对中的数据信号的边沿之间，或 在所选相位对的边缘之外，在其一侧或另一侧上。 如果时钟沿落在所选择的对之外，则控制信号选择另一对进行比较，并且重复处理，直到例如数据沿与时钟的正向边对齐。 在时钟频率等于两倍数据频率的情况下，可以在时钟的下降沿对数据进行采样。

    Deriving clocks in a memory system
    57.
    发明授权
    Deriving clocks in a memory system 失效
    在内存系统中派生时钟

    公开(公告)号：US07934115B2

    公开(公告)日：2011-04-26

    申请号：US12332396

    申请日：2008-12-11

    申请人： Frank D. Ferraiolo ,  Kevn C. Gower ,  Martin L. Schmatz

    发明人： Frank D. Ferraiolo ,  Kevn C. Gower ,  Martin L. Schmatz

    IPC分类号： G06F1/00

    CPC分类号： G06F13/4234 ,  G06F13/1689

    摘要： A computer program product and a hub device for deriving clocks in a memory system are provided. The computer program product includes a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for facilitating a method. The method includes receiving a reference oscillator clock at the hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.

    摘要翻译： 提供了一种用于在存储器系统中导出时钟的计算机程序产品和集线器设备。 计算机程序产品包括可由处理电路读取的存储介质，并且存储由处理电路执行以便于方法的指令。 该方法包括在集线器设备处接收参考振荡器时钟。 集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。 以基准时钟频率工作的基本时钟从参考振荡器时钟导出。 通过将基本时钟乘以存储器乘法器导出存储器接口时钟。 控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。 存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。

    Configurable Differential to Single Ended IO
    58.
    发明申请
    Configurable Differential to Single Ended IO 有权
    可配置差分至单端IO

    公开(公告)号：US20110075740A1

    公开(公告)日：2011-03-31

    申请号：US12568765

    申请日：2009-09-29

    申请人： Frank D. Ferraiolo ,  Kevin C. Gower ,  Robert B. Tremaine ,  Kenneth L. Wright

    发明人： Frank D. Ferraiolo ,  Kevin C. Gower ,  Robert B. Tremaine ,  Kenneth L. Wright

    IPC分类号： H04B3/00

    CPC分类号： H04L25/0272 ,  Y02D30/30

    摘要： An electronic system having a power efficient differential signal between a first and second electronic unit. A controller uses information, such as compliance with data transmission rate requirement and bit error rate (BER) versus a BER threshold to control power modes such that a minimal amount of power is required. Amplitude of transmission and single ended or differential transmission of data are examples of the power modes. The controller also factors in a failing phase in a differential signal in selecting a minimal power mode that satisfies the transmission rate requirement of the BER threshold.

    摘要翻译： 一种在第一和第二电子单元之间具有功率有效的差分信号的电子系统。 控制器使用诸如符合数据传输速率要求和误码率（BER）与BER阈值的信息来控制功率模式，使得需要最小量的功率。 传输幅度和数据的单端或差分传输是功率模式的例子。 控制器还在选择满足BER阈值的传输速率要求的最小功率模式时，在差分信号中导致故障相位。

    System, method and storage medium for bus calibration in a memory subsystem
    59.
    发明授权
    System, method and storage medium for bus calibration in a memory subsystem 失效
    用于内存子系统总线校准的系统，方法和存储介质

    公开(公告)号：US07590882B2

    公开(公告)日：2009-09-15

    申请号：US11780556

    申请日：2007-07-20

    申请人： Frank D. Ferraiolo ,  Kevin C. Gower

    发明人： Frank D. Ferraiolo ,  Kevin C. Gower

    IPC分类号： G06F1/12 ,  H04L9/18

    CPC分类号： G06F13/4239

    摘要： A cascaded interconnect system with one or more memory modules, a memory controller and a memory bus that utilizes periodic recalibration. The memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memory bus and provide scrambled data for use in the periodic recalibration.

    摘要翻译： 具有一个或多个存储器模块的级联互连系统，存储器控制器和利用定期重新校准的存储器总线。 存储器模块和存储器控制器通过存储器总线通过分组化的多传输接口直接互连，并提供用于定期重新校准的加扰数据。