公开(公告)号：US5471426A

公开(公告)日：1995-11-28

申请号：US830315

申请日：1992-01-31

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC classification number: G11C29/84

Abstract: An integrated circuit memory is disclosed which has its primary memory array arranged into blocks and which has redundant columns, each of which can replace a column in any one of the blocks. The redundant columns are selected by way of a redundant column decoder, associated with each column. A plurality of redundant sense amplifiers are each associated with selected redundant columns. Each of the redundant column decoders includes a set of address fuses for storing the column address responsive to which its associated redundant column is to be selected, and which are in series with pass gates which are turned on when redundancy is enabled, and turned off otherwise. This arrangement of address fuses and pass gates reduces and balances the loading of the decoder on the address lines, may be implemented with fewer transistors and thus in reduced chip area relative to conventional decoders, and also reduces the propagation delay through the decoder. The coupling of each redundant sense amplifier is controlled by a redundant multiplexer associated with each of the input/output terminals. Each redundant multiplexer receives the redundant column select signals from each redundant column decoder corresponding thereto, and includes fuses which indicate if its input/output terminal is to be placed in communication with its associated sense amplifier upon selection of a redundant column.

Abstract translation: 公开了一种集成电路存储器，其具有排列成块的主存储器阵列，并且具有冗余列，每个列可替代任何一个块中的列。 通过冗余列解码器选择冗余列，与列相关联。 多个冗余感测放大器各自与所选择的冗余列相关联。 冗余列解码器中的每一个包括一组地址熔丝，用于存储响应于其相关联的冗余列将要被选择的列地址，并且与冗余启用时导通的通过门串联，否则关闭 。 这种地址熔丝和通过门的排列减少并平衡了解码器在地址线上的负载，可以用较少的晶体管来实现，从而相对于传统解码器减少了芯片面积，并且还减少了通过解码器的传播延迟。 每个冗余读出放大器的耦合由与每个输入/输出端子相关联的冗余多路复用器控制。 每个冗余多路复用器从对应于其的每个冗余列解码器接收冗余列选择信号，并且包括指示其选择冗余列时是否将其输入/输出端子与其相关联的读出放大器通信的熔丝。

公开(公告)号：US5418756A

公开(公告)日：1995-05-23

申请号：US129763

申请日：1993-09-30

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C11/41 ,  G11C7/22 ,  G11C8/18 ,  G11C8/00

CPC classification number: G11C7/22 ,  G11C8/18

Abstract: An edge transition detector for a static access memory integrated circuit provides programmable operating characteristics. The edge transition detector includes a delay line taking a state signal received on a signal line as an input and generating a delayed state signal. An exclusive-OR gate takes the state signal and the delayed state signal as inputs and generating a transition pulse signal. An edge transition detector enable line connected to the exclusive-OR gate forces the output level of the exclusive-OR gate to match a predetermined logic level in a power efficient manner. An output buffer taking the transition pulse signal as its input and generating an edge detection pulse signal may also be modified to fusing, mask programming, or bonding to eliminate the edge transition detection signal.

Abstract translation: 用于静态存取存储器集成电路的边沿转换检测器提供可编程的操作特性。 边沿跃迁检测器包括延迟线，其将在信号线上接收的状态信号作为输入并产生延迟状态信号。 异或门将状态信号和延迟状态信号作为输入并产生转换脉冲信号。 连接到异或门的边沿跃迁检测器使能线强制异或门的输出电平以功率有效的方式匹配预定的逻辑电平。 将转换脉冲信号作为其输入并产生边沿检测脉冲信号的输出缓冲器也可以被修改为融合，掩模编程或接合以消除边沿转换检测信号。

公开(公告)号：US5408435A

公开(公告)日：1995-04-18

申请号：US984233

申请日：1992-11-20

Applicant: David C. McClure ,  Thomas A. Coker

Inventor： David C. McClure ,  Thomas A. Coker

IPC: G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  G11C7/00 ,  G11C11/40

CPC classification number: G11C29/46

Abstract: An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

Abstract translation: 具有正常操作模式和特殊操作模式的集成电路，例如特殊测试模式。 特殊测试模式通过一系列信号（例如终端的过电压偏移）而不是通过单个这样的偏移来实现，使得不经意地进入特殊测试模式的可能性较小，例如由于噪声或功率 降低和启动设备。 用于启用测试模式的电路包括一系列D型触发器，每个D型触发器在检测到过电压状态以及在另一个端子处施加的特定逻辑电平时被计时; 可以为多种特殊测试模式提供多个触发器系列。 附加功能包括提供上电复位电路，该电路在器件上电期间锁定进入测试模式。 进入测试模式的确认通过在器件未使能时在输出端子处呈现低阻抗来提供; 设备的芯片使能使设备退出测试模式。 一旦进入测试模式，器件的输出使能端可提供芯片使能功能。

公开(公告)号：US5379260A

公开(公告)日：1995-01-03

申请号：US128895

申请日：1993-09-30

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C29/50 ,  G11C29/00

CPC classification number: G11C29/50 ,  G11C11/41

Abstract: According to the present invention, a static random access memory (SRAM) cell which is normally supplied with a nominal supply voltage under normal operating conditions, may be supplied with a super supply voltage so that tests requiring high voltages and increased current levels, such as diagnostic and reliability "stress" tests may be performed. The super supply voltage is greater in magnitude than the nominal supply voltage, and may range from approximately 7 volts to 13 volts for SRAM cells requiring a positive voltage supply. The super supply voltage level may be controlled by a test mode or by a bond pad using existing power supply circuitry.

Abstract translation: 根据本发明，通常在正常工作条件下提供标称电源电压的静态随机存取存储器（SRAM）单元可以被提供有超级电源电压，以便需要高电压和增加的电流水平的测试，例如 可以进行诊断和可靠性“应力”测试。 超级电源电压的幅度大于额定电源电压，并且对于需要正电压电源的SRAM单元，其电压范围可以从大约7伏至13伏。 超级电源电压可以通过测试模式或通过使用现有电源电路的接合焊盘进行控制。

公开(公告)号：US5319347A

公开(公告)日：1994-06-07

申请号：US876851

申请日：1992-04-30

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G06F7/02 ,  G05B1/03

CPC classification number: G06F7/026

Abstract: A magnitude comparator suitable for use in a FIFO memory is modified to compare the magnitudes between any binary number and a fixed value. Bit comparators are divided into groups which generate compare output signals in parallel to one another, thereby reducing total magnitude comparator delay and resulting in faster operation. These compare output signals are fed into a control element which determines which compare output signal is allowed to pass through as the final compare output signal.

Abstract translation: 适用于FIFO存储器的幅度比较器被修改以比较任何二进制数和固定值之间的幅度。 位比较器被分成组，其彼此并行地生成比较输出信号，从而减小总幅度比较器延迟并导致更快的操作。 这些比较输出信号被馈送到控制元件，该控制元件确定哪个比较输出信号被允许通过作为最终的比较输出信号。

公开(公告)号：US5305268A

公开(公告)日：1994-04-19

申请号：US627049

申请日：1990-12-13

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C11/41 ,  G11C11/419 ,  G11C7/00

CPC classification number: G11C11/419

Abstract: A static random-access memory is disclosed which utilizes bit line pairs for each column of memory cells for communication of data between external data terminals and the memory cells. A precharge transistor is connected between each bit line and a precharge voltage, for example V.sub.cc, and an equilibration transistor is connected between the bit lines in each bit line pair. The precharge and equilibration transistors are controlled according to selection of the column, so that all columns which are not selected by the column address are precharged and equilibrated, including the unselected columns in the same sub-array as the selected columns. In an additional embodiment of the invention, a data transition detection circuit also controls the precharge and equilibration transistors, so that the precharge and equilibration transistors for the selected columns are turned on responsive to an input data transition during a write operation; this assists the write drivers in more quickly writing the new data onto the bit lines.

Abstract translation: 公开了一种静态随机存取存储器，其利用存储器单元的每列的位线对用于在外部数据端子和存储器单元之间进行数据通信。 预充电晶体管连接在每个位线和预充电电压（例如Vcc）之间，并且平衡晶体管连接在每个位线对中的位线之间。 根据列的选择来控制预充电和平衡晶体管，使得未被列地址选择的所有列被预充电和平衡，包括与所选列相同的子阵列中的未选择的列。 在本发明的另外的实施例中，数据转换检测电路还控制预充电和平衡晶体管，使得响应于写操作期间的输入数据转换，所选列的预充电和平衡晶体管导通; 这有助于写入驱动程序更快地将新数据写入位线。

公开(公告)号：US5297090A

公开(公告)日：1994-03-22

申请号：US627050

申请日：1990-12-13

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C11/41 ,  G11C11/419 ,  G11C7/00 ,  G11C11/34

CPC classification number: G11C11/419

Abstract: A static random-access memory is disclosed which utilizes bit line pairs for each column of memory cells for communication of data between external data terminals and the memory cells. A precharge transistor is connected between each bit line and a precharge voltage, for example V , and an equilibration transistor is connected between the bit lines in each bit line pair. The precharge and equilibration transistors are controlled according to selection of the column, so that all columns which are not selected by the column address are precharged and equilibrated, including the unselected columns in the same sub-array as the selected columns. In an additional embodiment of the invention, a data transition detection circuit also controls the precharge and equilibration transistors, so that the precharge and equilibration transistors for the selected columns are turned on responsive to an input data transition during a write operation; this assists the write drivers in more quickly writing the new data onto the bit lines.

Abstract translation: 公开了一种静态随机存取存储器，其利用存储器单元的每列的位线对用于在外部数据端子和存储器单元之间进行数据通信。 预充电晶体管连接在每个位线和预充电电压之间，例如V，并且平衡晶体管连接在每个位线对中的位线之间。 根据列的选择来控制预充电和平衡晶体管，使得未被列地址选择的所有列被预充电和平衡，包括与所选列相同的子阵列中的未选择的列。 在本发明的另外的实施例中，数据转换检测电路还控制预充电和平衡晶体管，使得响应于写操作期间的输入数据转换，所选列的预充电和平衡晶体管导通; 这有助于写入驱动程序更快地将新数据写入位线。

公开(公告)号：US5295102A

公开(公告)日：1994-03-15

申请号：US830237

申请日：1992-01-31

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC classification number: G11C29/83 ,  G11C29/846 ,  G11C29/781

Abstract: An integrated circuit memory is disclosed which has its primary memory array arranged into blocks and which has redundant columns, each of which can replace a column in any one of the blocks. The redundant columns are selected by way of a redundant column decoder associated with each column, each of which includes a set of address fuses into which an address is programmed, responsive to which its associated redundant column is to be selected. A plurality of redundant sense amplifiers are each associated with selected redundant columns, and are each controlled to begin the sense operation prior to propagation of the address signal through the redundant column decoders and summing circuitry. In the event that the received memory address does not match any of the programmed values in the redundant column decoders associated with a redundant sense amplifier, the sense operation is terminated. In this way, the sense operation is not delayed by the additional delay required for redundant decoding and propagation of the redundant address signals, and thus the access time penalty for accessing a redundant memory cell is much reduced or eliminated. The coupling of each redundant sense amplifier is controlled by a redundant multiplexer associated with each of the input/output terminals. Each redundant multiplexer receives the redundant column select signals from each associated redundant column decoder, and includes fuses which indicate if its input/output terminal is to be placed in communication with its associated sense amplifier upon selection of a redundant column.

Abstract translation: 公开了一种集成电路存储器，其具有排列成块的主存储器阵列，并且具有冗余列，每个列可替代任何一个块中的列。 冗余列通过与每个列相关联的冗余列解码器来选择，每个列包括一组地址熔丝，地址被编程到其中，响应于哪个相关联的冗余列被选择。 多个冗余读出放大器各自与所选择的冗余列相关联，并且每个冗余读出放大器都被控制以在通过冗余列解码器和求和电路传播地址信号之前开始感测操作。 在接收到的存储器地址与冗余读出放大器相关联的冗余列解码器中的任何编程值不匹配的情况下，感测操作终止。 以这种方式，由于冗余解码和冗余地址信号的传播所需的附加延迟，感测操作不会延迟，因此大大减少或消除了用于访问冗余存储器单元的访问时间损失。 每个冗余读出放大器的耦合由与每个输入/输出端子相关联的冗余多路复用器控制。 每个冗余多路复用器接收来自每个相关联的冗余列解码器的冗余列选择信号，并且包括指示其选择冗余列时是否将其输入/输出端子与其相关联的读出放大器通信的熔丝。

公开(公告)号：US5267210A

公开(公告)日：1993-11-30

申请号：US25894

申请日：1993-03-03

Applicant: David C. McClure ,  Mark A. Lysinger

Inventor： David C. McClure ,  Mark A. Lysinger

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/20 ,  G11C11/412 ,  G11C11/40

CPC classification number: G11C11/412 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/20

Abstract: A static random access memory having multiple I/Os includes a memory array (10) of memory cells (42) with columns that are selectively clearable as a function of the associated I/O. The columns are arranged in pairs (34) with each column in the pair (34) associated with the same I/O. A clear signal is input thereto on a line (28) and driven by a driver (30). The clear signal is only associated with the pairs (34) associated with a selected I/O. The remaining columns of memory cells associated with unselected I/Os are not cleared.

Abstract translation: 具有多个I / O的静态随机存取存储器包括存储器单元（42）的存储器阵列（10），所述存储器单元（42）具有作为相关I / O的函数可选择地清零的列。 这些列以成对（34）排列，成对（34）中的每个列与相同的I / O相关联。 在线路（28）上输入清除信号并由驱动器（30）驱动。 清除信号仅与与选择的I / O相关联的对（34）相关联。 与未选择的I / O相关联的其余存储单元列不会被清除。

公开(公告)号：US5265100A

公开(公告)日：1993-11-23

申请号：US552567

申请日：1990-07-13

Applicant: David C. McClure ,  Thomas A. Coker

Inventor： David C. McClure ,  Thomas A. Coker

IPC: G11C29/00 ,  G11C29/28 ,  G11C29/34 ,  G11C29/38 ,  G01R31/28

CPC classification number: G11C29/28 ,  G11C29/34 ,  G11C29/38

Abstract: An integrated circuit memory is disclosed which has a parallel test read mode. The memory includes comparators for comparing multiple data words, on a bit-by-bit basis, during the parallel read mode, with the result of the comparison used to enable or disable the output buffers. In test mode, in the event of a failed parallel test comparison, the comparator causes the output buffers to go into a high-impedance state; for a passing parallel test, the actual data state is presented by the output terminals The comparison circuitry is in parallel with the output data path, so that the output data path is not adversely affected by the test circuitry, and so that the access time in test mode is the same as the access time during normal operation (assuming a passing test). The technique may be adapted to wide parallel test schemes.