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    Automatically Linking Partitions on a Tape Media Device
    51.
    发明申请
    Automatically Linking Partitions on a Tape Media Device 有权
    自动链接磁带介质设备上的分区

    公开(公告)号：US20110107023A1

    公开(公告)日：2011-05-05

    申请号：US12608161

    申请日：2009-10-29

    Applicant: Ryan P. McCallister ,  David Howard

    Inventor： Ryan P. McCallister ,  David Howard

    IPC: G06F12/00 ,  G06F12/02 ,  G06F12/16

    CPC classification number: G06F3/0664 ,  G06F3/0608 ,  G06F3/0644 ,  G06F3/0652 ,  G06F3/0665 ,  G06F3/0682 ,  G06F3/0686

    Abstract: A system and method for automatically linking partitions on storage media for use within a storage management system is provided to minimize wasted space on the storage media, the time and expense traditionally spent reclaiming partitions containing invalid data, and the computer processing capability required to write data to and read data from the storage media. The storage management system includes a partitioned storage tape, a host application running on a server, and an archive device. The host application is operative to track location information for each host file or data object written to the storage tape. Using the location information, the host application is able to identify one or more “free” or writable partitions that are created on the storage tape as host files expire. Moreover, when writing host files to the storage tape, the archive device is operative to automatically link the writable partitions to form logical volumes such that when reading host files from the storage tape, the archive device can automatically navigate through the logical volumes.

    Abstract translation: 提供了一种用于自动链接存储介质上用于存储管理系统中的分区的系统和方法，以最小化存储介质上浪费的空间，传统上花费回收包含无效数据的分区的时间和费用以及写入数据所需的计算机处理能力 从存储介质读取和读取数据。 存储管理系统包括分区存储磁带，在服务器上运行的主机应用程序和归档设备。 主机应用程序可操作以跟踪写入存储磁带的每个主机文件或数据对象的位置信息。 使用位置信息，主机应用程序能够识别在主机文件过期时在存储磁带上创建的一个或多个“空闲”或可写分区。 此外，当将主机文件写入存储磁带时，归档设备可操作以自动链接可写分区以形成逻辑卷，使得当从存储磁带读取主机文件时，归档设备可以自动导航逻辑卷。

    System and method for 3D radar image rendering
    52.
    发明授权
    System and method for 3D radar image rendering 有权
    3D雷达图像渲染的系统和方法

    公开(公告)号：US07688248B2

    公开(公告)日：2010-03-30

    申请号：US12277111

    申请日：2008-11-24

    Applicant: Jack Cross ,  Theodore Bosworth ,  Craig Chapman ,  David Howard

    Inventor： Jack Cross ,  Theodore Bosworth ,  Craig Chapman ,  David Howard

    IPC: G01S7/20

    CPC classification number: G06T15/10 ,  G01S7/20 ,  G01S13/89 ,  G01S13/94 ,  G06T17/05

    Abstract: A 3D rendered image of a radar-scanned terrain surface is provided from a radar return signal from the surface, wherein the return signal includes data indicative of azimuth, elevation, and range of a radar-illuminated area of the surface. The data are processed for transformation into X, Y, and Z coordinates. The X and Y coordinates corresponding to each illuminated area are triangulated so as to create a mesh of triangles representing the terrain surface, each of the triangles in the mesh being defined by a vertex triplet. 3D imaging information (grey scale shading and/or coloring information) is added to each triangle in the mesh, based on the amplitude of the radar return signal from the coordinates represented by each vertex in the triplet and the value of the Z coordinate at each vertex, so as to form the 3D rendered image.

    Abstract translation: 雷达扫描地形表面的3D渲染图像从表面的雷达返回信号提供，其中返回信号包括指示表面的雷达照明区域的方位角，仰角和范围的数据。 处理数据以转换为X，Y和Z坐标。 对应于每个照明区域的X和Y坐标进行三角测量，以创建表示地形表面的三角形网格，网格中的每个三角形由顶点三元组定义。 基于由三重态中的每个顶点表示的坐标的雷达返回信号的幅度和每个三角形中的Z坐标的值，将3D成像信息（灰度阴影和/或着色信息）添加到网格中的每个三角形 顶点，以形成3D渲染图像。

    System and method for 3D radar image rendering
    53.
    发明授权
    System and method for 3D radar image rendering 有权
    3D雷达图像渲染的系统和方法

    公开(公告)号：US07456779B2

    公开(公告)日：2008-11-25

    申请号：US11469400

    申请日：2006-08-31

    Applicant: Jack Cross ,  Theodore Bosworth ,  Craig Chapman ,  David Howard

    Inventor： Jack Cross ,  Theodore Bosworth ,  Craig Chapman ,  David Howard

    IPC: G01S7/20

    CPC classification number: G06T15/10 ,  G01S7/20 ,  G01S13/89 ,  G01S13/94 ,  G06T17/05

    Abstract: A 3D rendered image of a radar-scanned terrain surface is provided from a radar return signal from the surface, wherein the return signal includes data indicative of azimuth, elevation, and range of a radar-illuminated area of the surface. The data are processed for transformation into X, Y, and Z coordinates. The X and Y coordinates corresponding to each illuminated area are triangulated so as to create a mesh of triangles representing the terrain surface, each of the triangles in the mesh being defined by a vertex triplet. 3D imaging information (grey scale shading and/or coloring information) is added to each triangle in the mesh, based on the amplitude of the radar return signal from the coordinates represented by each vertex in the triplet and the value of the Z coordinate at each vertex, so as to form the 3D rendered image.

    Abstract translation: 雷达扫描地形表面的3D渲染图像从表面的雷达返回信号提供，其中返回信号包括指示表面的雷达照明区域的方位角，仰角和范围的数据。 处理数据以转换为X，Y和Z坐标。 对应于每个照明区域的X和Y坐标进行三角测量，以创建表示地形表面的三角形网格，网格中的每个三角形由顶点三元组定义。 基于由三重态中的每个顶点表示的坐标的雷达返回信号的幅度和每个三角形中的Z坐标的值，将3D成像信息（灰度阴影和/或着色信息）添加到网格中的每个三角形 顶点，以形成3D渲染图像。

    Method for fabricating a MIM capacitor high-K dielectric for increased capacitance density and related structure
    55.
    发明授权
    Method for fabricating a MIM capacitor high-K dielectric for increased capacitance density and related structure 有权
    用于制造用于增加电容密度和相关结构的MIM电容器高K电介质的方法

    公开(公告)号：US07220639B2

    公开(公告)日：2007-05-22

    申请号：US11121360

    申请日：2005-05-03

    Applicant: Hadi Abdul-Ridha ,  David Howard

    Inventor： Hadi Abdul-Ridha ,  David Howard

    IPC: H01L21/8242

    CPC classification number: H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a high-k dielectric layer comprising AlNX (aluminum nitride) on the first interconnect layer. The method further includes depositing a layer of MIM capacitor metal on the high-k dielectric layer. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the first interconnect metal layer, the high-k dielectric layer, and the layer of MIM capacitor metal can be deposited in a PVD process chamber. The method further includes etching the high-k dielectric layer to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor.

    Abstract translation: 根据本发明的一个实施例，在半导体管芯中制造MIM电容器的方法包括沉积第一互连金属层的步骤。 该方法还包括在第一互连层上沉积包含AlN（N 2）的高k电介质层。 该方法还包括在高k电介质层上沉积MIM电容器金属层。 该方法还包括蚀刻MIM电容器金属层以形成MIM电容器的上电极。 根据该示例性实施例，第一互连金属层，高k电介质层和MIM电容器金属层可以沉积在PVD处理室中。 该方法还包括蚀刻高k电介质层以形成MIM电容器介电段并蚀刻第一互连金属层以形成MIM电容器的下电极。

    On-chip inductors
    56.
    发明授权
    On-chip inductors 有权
    片上电感

    公开(公告)号：US07173318B2

    公开(公告)日：2007-02-06

    申请号：US09754806

    申请日：2001-01-02

    Applicant: Q Z Liu ,  Bin Zhao ,  David Howard

    Inventor： Q Z Liu ,  Bin Zhao ,  David Howard

    IPC: H01L29/00

    CPC classification number: H01L28/10 ,  H01L27/08

    Abstract: Method for fabrication of on-chip inductors and related structure are disclosed. According to one embodiment, inductors are formed by patterning conductors within a certain dielectric layer in a semiconductor die. Thereafter, the entire dielectric layer in the semiconductor die is subjected to a blanket implantation or sputtering of high permeability material. According to another embodiment, a first area in a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor die includes a patterned conductor which is to be used as an inductor. The patterned conductor is also covered, for example, with photoresist. The second area, excluding the covered patterned conductor, is subjected to implantation or sputtering of high permeability material. According to yet another embodiment, a first area of a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor area includes a patterned conductor which is to be used as an inductor. This second area, including the patterned conductor, is subjected to implantation or sputtering of high permeability material. The implantation or sputtering of high permeability materials result in the inductors having much higher inductance values than they would otherwise have.

    Abstract translation: 公开了片上电感器的制造方法和相关结构。 根据一个实施例，电感器通过在半导体管芯内的某个介电层内图案化导体而形成。 此后，对半导体管芯中的整个电介质层进行高导磁率材料的覆盖注入或溅射。 根据另一实施例，半导体管芯中的第一区域例如被光致抗蚀剂覆盖。 半导体管芯中的第二区域包括用作电感器的图案化导体。 图案化的导体也例如用光致抗蚀剂覆盖。 除了被覆盖的图案导体之外的第二区域经受高磁导率材料的注入或溅射。 根据另一个实施例，半导体管芯的第一区域例如被光致抗蚀剂覆盖。 半导体区域中的第二区域包括用作电感器的图案化导体。 包括图案化导体的该第二区域经受高磁导率材料的注入或溅射。 高磁导率材料的注入或溅射导致电感器的电感值高于原来的电感值。

    Apparatus and process for pressing and cooking food product logs
    57.
    发明授权
    Apparatus and process for pressing and cooking food product logs 失效
    用于压制和烹饪食品原料的设备和方法

    公开(公告)号：US07069840B1

    公开(公告)日：2006-07-04

    申请号：US10442743

    申请日：2003-05-21

    Applicant: David Howard

    Inventor： David Howard

    IPC: A22C7/00 ,  B30B7/02

    CPC classification number: A22C7/0053 ,  Y10S100/91

    Abstract: An apparatus and a method for pressing and cooking and/or chilling food product logs. The apparatus and method comprise or use a tower press which has vertically compressible tiers and is positioned and mounted at one location for selectively elevating and lowering the tower press. The apparatus and method further comprise or use a container positioned at the same location such that the tower press can be lowered into the container for cooking and/or chilling the food product logs. The tower press can also be elevated out of the container for loading and removing food product logs from the vertically compressible tiers.

    Abstract translation: 用于压制和烹饪和/或冷冻食品原料的设备和方法。 该装置和方法包括或使用具有可垂直压缩层的塔式压榨机，并且其定位并安装在一个位置以选择性地升降塔式压榨机。 该装置和方法还包括或使用位于相同位置处的容器，使得塔式压榨机可以下降到容器中用于烹饪和/或冷冻食品原料。 塔式压榨机也可以从容器中提升出来，以便从垂直压缩层中装载和除去食品原料。

    Method for fabricating a metal resistor in an IC chip and related structure
    58.
    发明授权
    Method for fabricating a metal resistor in an IC chip and related structure 有权
    IC芯片中金属电阻器的制造方法及相关结构

    公开(公告)号：US06943414B2

    公开(公告)日：2005-09-13

    申请号：US10073751

    申请日：2002-02-09

    Applicant: Arjun Kar Roy ,  David Howard ,  Q.Z. Liu

    Inventor： Arjun Kar Roy ,  David Howard ,  Q.Z. Liu

    IPC: H01L21/02 ,  H01L27/08 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC classification number: H01L28/24 ,  H01L27/0802

    Abstract: According to one exemplary embodiment, an integrated circuit chip comprises a first interconnect metal layer. The integrated circuit chip further comprises a first intermediate dielectric layer situated over the first interconnect metal layer. The integrated circuit chip further comprises a metal resistor situated over the first intermetallic dielectric layer and below a second intermetallic dielectric layer. The integrated circuit chip further comprises a second interconnect metal layer over the second intermetallic dielectric layer. The integrated circuit chip further comprises a first intermediate via connected to first terminal of the metal resistor, where the first intermediate via is further connected to a first metal segment patterned in the second interconnect metal layer. The integrated circuit chip further comprises a second intermediate via connected to a second terminal of the metal resistor, where the second intermediate via is further connected to a second metal segment patterned in the second interconnect metal layer.

    Abstract translation: 根据一个示例性实施例，集成电路芯片包括第一互连金属层。 集成电路芯片还包括位于第一互连金属层上的第一中间电介质层。 集成电路芯片还包括位于第一金属间介电层之上并位于第二金属间介电层下方的金属电阻器。 集成电路芯片还包括在第二金属间介电层上的第二互连金属层。 集成电路芯片还包括连接到金属电阻器的第一端子的第一中间通孔，其中第一中间通孔进一步连接到在第二互连金属层中图案化的第一金属段。 集成电路芯片还包括连接到金属电阻器的第二端子的第二中间通路，其中第二中间通路进一步连接到在第二互连金属层中图案化的第二金属段。

    High density composite MIM capacitor with reduced voltage dependence in semiconductor dies
    59.
    发明授权
    High density composite MIM capacitor with reduced voltage dependence in semiconductor dies 有权
    具有降低电压依赖性的半导体芯片的高密度复合MIM电容器

    公开(公告)号：US06680521B1

    公开(公告)日：2004-01-20

    申请号：US10410937

    申请日：2003-04-09

    Applicant: Arjun Kar-Roy ,  Marco Racanelli ,  David Howard

    Inventor： Arjun Kar-Roy ,  Marco Racanelli ,  David Howard

    IPC: H01L2900

    CPC classification number: H01L28/40 ,  H01L21/76838 ,  H01L27/0805

    Abstract: According to a disclosed embodiment, a composite MIM capacitor comprises a lower electrode of a lower MIM capacitor situated in a lower interconnect metal layer of a semiconductor die. The composite MIM capacitor further comprises an upper electrode of the lower MIM capacitor situated within a lower interlayer dielectric, where the lower interlayer dielectric separates the lower interconnect metal layer from an upper interconnect metal layer. A lower electrode of the upper MIM capacitor is situated in the upper interconnect metal layer. An upper electrode of the upper MIM capacitor is situated within the upper interlayer dielectric which is, in turn, situated over the upper interconnect metal layer. The upper electrode of the lower MIM capacitor is connected to the lower electrode of the upper MIM capacitor while the lower electrode of the lower MIM capacitor is connected to the upper electrode of the upper MIM capacitor.

    Abstract translation: 根据所公开的实施例，复合MIM电容器包括位于半导体管芯的下互连金属层中的下MIM电容器的下电极。 复合MIM电容器还包括位于下层间电介质中的下MIM电容器的上电极，其中下层间电介质将下互连金属层与上互连金属层分开。 上MIM电容器的下电极位于上互连金属层中。 上MIM电容器的上电极位于上层间电介质中，其又位于上互连金属层上。 下MIM电容器的上电极连接到上MIM电容器的下电极，而下MIM电容器的下电极连接到上MIM电容器的上电极。

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