公开(公告)号：US08080453B1

公开(公告)日：2011-12-20

申请号：US10186453

申请日：2002-06-28

Applicant: Alain Blosse ,  Krishnaswamy Ramkumar

Inventor： Alain Blosse ,  Krishnaswamy Ramkumar

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823475 ,  H01L21/823871 ,  H01L29/78

Abstract: A semiconductor structure includes a semiconductor substrate, a gate layer containing silicon on the semiconductor substrate, a metallic layer on the gate layer, and a nitride layer on the metallic layer. The gate layer contains a P+ region and an N+ region.

Abstract translation: 半导体结构包括半导体衬底，在半导体衬底上含有硅的栅极层，栅极层上的金属层和金属层上的氮化物层。 栅极层包含P +区和N +区。

公开(公告)号：US20090032863A1

公开(公告)日：2009-02-05

申请号：US12005813

申请日：2007-12-27

Applicant: Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

Inventor： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/3143 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518

Abstract: A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O2 and the reoxidation is performed with NO.

Abstract translation: 一种用于形成非易失性俘获电荷存储装置的隧道层的方法及其制成的制品。 该方法包括多次氧化和氮化操作，以提供比纯二氧化硅隧道层更高的介电常数，但是具有比在衬底界面处具有氮的隧穿层更少的氢和氮阱。 该方法提供了SONOS型设备中改进的存储器窗口。 在一个实施方案中，该方法包括氧化，氮化，再氧化和重新染色。 在一个实施方案中，首先用O 2进行氧化，并用NO进行再氧化。

公开(公告)号：US20080290399A1

公开(公告)日：2008-11-27

申请号：US11904475

申请日：2007-09-26

Applicant: Sagy Levy ,  Fredrick B. Jenne ,  Krishnaswamy Ramkumar

Inventor： Sagy Levy ,  Fredrick B. Jenne ,  Krishnaswamy Ramkumar

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/66833

Abstract: A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source/drain regions. A gate stack is above the substrate over the channel region and between the pair of source/drain regions. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.

Abstract translation: 描述了非易失性电荷陷阱存储器件。 该器件包括具有沟道区和一对源极/漏极区的衬底。 栅极堆叠在沟道区域上方之间以及在一对源极/漏极区域之间的衬底之上。 栅极堆叠包括具有第一氘化层的多层电荷捕获区域。 多层电荷俘获区域还可以包括不含氘的电荷俘获层。

公开(公告)号：US20080166893A1

公开(公告)日：2008-07-10

申请号：US11969125

申请日：2008-01-03

Applicant: Jeong Soo Byun ,  Krishnaswamy Ramkumar

Inventor： Jeong Soo Byun ,  Krishnaswamy Ramkumar

IPC: H01L21/321

CPC classification number: H01L21/28247 ,  H01L21/28044 ,  H01L29/4925

Abstract: A method of forming a semiconductor structure includes oxidizing a gate stack at a temperature of at most 600° C. with a plasma prepared from a gas mixture. The gas mixture includes an oxygen-containing gas and ammonia, and the gate stack is on a semiconductor substrate. The gate stack contains a gate layer, a conductive layer on the gate layer, a metal layer on the conductive layer, and a capping layer on the metal layer.

Abstract translation: 形成半导体结构的方法包括用气体混合物制备的等离子体在至多600℃的温度下氧化栅极叠层。 气体混合物包括含氧气体和氨，并且栅极堆叠在半导体衬底上。 栅极堆叠包含栅极层，栅极层上的导电层，导电层上的金属层和金属层上的覆盖层。

公开(公告)号：US07390750B1

公开(公告)日：2008-06-24

申请号：US11087924

申请日：2005-03-23

Applicant: Krishnaswamy Ramkumar ,  Alain P. Blosse ,  James A. Hunter

Inventor： Krishnaswamy Ramkumar ,  Alain P. Blosse ,  James A. Hunter

IPC: H01L21/302

CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132

Abstract: A method is provided which includes forming a hardmask feature adjacent to a patterned sacrificial structure of a semiconductor topography, selectively removing the patterned sacrificial structure to expose a lower layer and etching exposed portions of the lower layer in alignment with the hardmask feature. In some embodiments, forming the hardmask feature may include conformably depositing a hardmask material above the patterned sacrificial structure and lower layer as well as blanket etching the hardmask material such that upper surfaces of the patterned sacrificial structure and portions of the lower layer are exposed and portions of the hardmask material remain along sidewalls of the patterned sacrificial structure. The method may be applied to produce an exemplary semiconductor topography including a plurality of gate structures each having a width less than approximately 70 nm, wherein a variation of the widths among the plurality of gate structures is less than approximately 10%.

Abstract translation: 提供了一种方法，其包括形成与半导体形貌的图案化牺牲结构相邻的硬掩模特征，选择性地去除图案化的牺牲结构以暴露下层并蚀刻与硬掩模特征对准的下层的暴露部分。 在一些实施例中，形成硬掩模特征可以包括在图案化的牺牲结构和下层之上顺应地沉积硬掩模材料，以及橡皮布蚀刻硬掩模材料，使得图案化的牺牲结构的上表面和下层的部分被暴露， 硬掩模材料保留在图案化牺牲结构的侧壁上。 该方法可以应用于产生包括多个栅极结构的示例性半导体形貌，每个栅极结构的宽度小于约70nm，其中多个栅极结构之间的宽度变化小于约10％。

公开(公告)号：US07384833B2

公开(公告)日：2008-06-10

申请号：US11350160

申请日：2006-02-07

Applicant: Igor Polishchuk ,  Krishnaswamy Ramkumar ,  Sagy Charel Levy

Inventor： Igor Polishchuk ,  Krishnaswamy Ramkumar ,  Sagy Charel Levy

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a stress liner over the active region. This leaves the stress liner mostly on the sidewall and top of the gate of the MOS transistor. Removing portions of the stress liner over the active region substantially removes the lateral component of the strain imparted by the stress liner on the substrate, allowing for improved drive current without substantially degrading a complementary MOS transistor.

Abstract translation: 在一个实施例中，通过电介质层形成自对准接触（SAC）沟槽结构以暴露MOS晶体管的有源区。 SAC沟槽结构不仅暴露用于电连接的有源区，而且还去除了有源区上的应力衬垫的部分。 这使得应力衬垫主要在MOS晶体管的侧壁和顶部上方。 在有源区上去除应力衬垫的部分基本上消除了由衬底上的应力衬垫施加的应变的横向分量，从而允许改进的驱动电流而不会使互补MOS晶体管基本上降级。

公开(公告)号：US07256087B1

公开(公告)日：2007-08-14

申请号：US11018422

申请日：2004-12-21

Applicant: Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

Inventor： Sharmin Sadoughi ,  Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Igor Polishchuk ,  Maroun Khoury

IPC: H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/823842

Abstract: In one embodiment, an integrated circuit includes a PMOS transistor having a gate stack comprising a P+ doped gate polysilicon layer and a nitrided gate oxide (NGOX) layer. The NGOX layer may be over a silicon substrate. The integrated circuit further includes an interconnect line formed over the transistor. The interconnect line includes a hydrogen getter material and may comprise a single material or stack of materials. The interconnect line advantageously getters hydrogen (e.g., H2 or H2O) that would otherwise be trapped in the NGOX layer/silicon substrate interface, thereby improving the negative bias temperature instability (NBTI) lifetime of the transistor.

Abstract translation: 在一个实施例中，集成电路包括具有包括P +掺杂栅极多晶硅层和氮化栅极氧化物（NGOX）层的栅极堆叠的PMOS晶体管。 NGOX层可以在硅衬底之上。 集成电路还包括形成在晶体管上的互连线。 互连线包括吸氢材料，并且可以包括单一材料或材料堆。 互连线有利地吸收否则将被捕获在NGOX层/硅衬底界面中的氢（例如，H 2 H 2或H 2 O 2），从而提高负偏压温度 晶体管的不稳定性（NBTI）寿命。

公开(公告)号：US07227212B1

公开(公告)日：2007-06-05

申请号：US11021220

申请日：2004-12-23

Applicant: Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  James Hunter ,  Thurman J. Rodgers ,  Mike Bruner ,  Klyoko Ikeuchi

Inventor： Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  James Hunter ,  Thurman J. Rodgers ,  Mike Bruner ,  Klyoko Ikeuchi

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/5227 ,  H01L23/53223 ,  H01L23/53238 ,  H01L28/87 ,  H01L2924/0002 ,  Y10S257/924 ,  H01L2924/00

Abstract: In one embodiment, a sacrificial layer is deposited over a base layer. The sacrificial layer is used to define a subsequently formed floating metal structure. The floating metal structure may be anchored into the base layer. Once the floating metal structure is formed, the sacrificial layer surrounding the floating metal structure is etched to create a unity-k dielectric region separating the floating metal structure from the base layer. The unity-k dielectric region also separates the floating metal structure from another floating metal structure. In one embodiment, a noble gas fluoride such as xenon difluoride is used to etch a sacrificial layer of polycrystalline silicon.

Abstract translation: 在一个实施例中，牺牲层沉积在基底层上。 牺牲层用于限定随后形成的浮动金属结构。 浮动金属结构可以锚定到基层中。 一旦形成了浮动金属结构，则蚀刻围绕浮动金属结构的牺牲层，以产生将浮动金属结构与基底层分开的单位k介电区域。 unity-k电介质区域还将浮动金属结构与另一个浮动金属结构分离。 在一个实施方案中，使用惰性气体氟化物如二氟化氙来蚀刻多晶硅的牺牲层。

公开(公告)号：US07192867B1

公开(公告)日：2007-03-20

申请号：US10184336

申请日：2002-06-26

Applicant: Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Seurabh Dutta Chowdhury ,  Michal Efrati Fastow

Inventor： Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Seurabh Dutta Chowdhury ,  Michal Efrati Fastow

IPC: H01L21/302

CPC classification number: H01L21/76831 ,  H01L21/76814

Abstract: In one embodiment, a passivation level includes a low-k dielectric. To prevent the low-k dielectric from absorbing moisture when exposed to air, exposed portions of the low-k dielectric are covered with spacers. As can be appreciated, this facilitates integration of low-k dielectrics in passivation levels. Low-k dielectrics in passivation levels help lower capacitance on metal lines, thereby reducing RC delay and increasing signal propagation speeds.

Abstract translation: 在一个实施例中，钝化层包括低k电介质。 为了防止低k电介质暴露于空气时吸收水分，低k电介质的暴露部分被间隔物覆盖。 可以理解，这有助于低k电介质在钝化层中的集成。 钝化层中的低k电介质有助于降低金属线路上的电容，从而减少RC延迟并增加信号传播速度。

公开(公告)号：US06835616B1

公开(公告)日：2004-12-28

申请号：US10059823

申请日：2002-01-29

Applicant: Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  James Hunter ,  Thurman J. Rodgers ,  Mike Bruner ,  Klyoko Keuchi

Inventor： Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  James Hunter ,  Thurman J. Rodgers ,  Mike Bruner ,  Klyoko Keuchi

IPC: H01L218242

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/5227 ,  H01L23/53223 ,  H01L23/53238 ,  H01L28/87 ,  H01L2924/0002 ,  Y10S257/924 ,  H01L2924/00

Abstract: In one embodiment, a sacrificial layer is deposited over a base layer. The sacrificial layer is used to define a subsequently formed floating metal structure. The floating metal structure may be anchored into the base layer. Once the floating metal structure is formed, the sacrificial layer surrounding the floating metal structure is etched to create a unity-k dielectric region separating the floating metal structure from the base layer. The unity-k dielectric region also separates the floating metal structure from another floating metal structure. In one embodiment, a noble gas fluoride such as xenon difluoride is used to etch a sacrificial layer of polycrystalline silicon.

Abstract translation: 在一个实施例中，牺牲层沉积在基底层上。 牺牲层用于限定随后形成的浮动金属结构。 浮动金属结构可以锚定到基层中。 一旦形成了浮动金属结构，则蚀刻围绕浮动金属结构的牺牲层，以产生将浮动金属结构与基底层分开的单位k介电区域。 unity-k电介质区域还将浮动金属结构与另一个浮动金属结构分离。 在一个实施方案中，使用惰性气体氟化物如二氟化氙来蚀刻多晶硅的牺牲层。