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    Wafer-level seal for non-silicon-based devices
    3.
    发明授权
    Wafer-level seal for non-silicon-based devices 有权
    非硅基器件的晶圆级密封

    公开(公告)号：US07466022B2

    公开(公告)日：2008-12-16

    申请号：US11041857

    申请日：2005-01-24

    申请人： Gregory D. Miller ,  Mike Bruner

    发明人： Gregory D. Miller ,  Mike Bruner

    IPC分类号： H01L23/14 ,  H01L41/22 ,  C23F1/00

    CPC分类号： B81C1/00293 ,  B81C2203/0136 ,  H03H3/08 ,  H03H9/02921 ,  H03H9/02984 ,  H03H9/1092 ,  Y10T29/42 ,  Y10T29/49005 ,  Y10T29/49011 ,  Y10T29/4908 ,  Y10T29/49126

    摘要： One embodiment disclosed relates to a method for sealing an active area of a non-silicon-based device on a wafer. The method includes providing a sacrificial material over at least the active area of the non-silicon-based device, depositing a seal coating over the wafer so that the seal coating covers the sacrificial material, and replacing the sacrificial material with a target atmosphere. Another embodiment disclosed relates to a non-silicon-based device sealed at the wafer level (i.e. prior to separation of the die from the wafer). The device includes an active area to be protected, a contact area, and a lithographically-formed structure sealing at least the active area and leaving at least a portion of the contact area exposed.

    摘要翻译： 公开的一个实施例涉及一种用于密封晶片上的非硅基器件的有源区域的方法。 该方法包括在非硅基器件的至少有源区域上提供牺牲材料，在晶片上沉积密封涂层，使得密封涂层覆盖牺牲材料，并用目标气氛代替牺牲材料。 所公开的另一实施例涉及在晶片级（即，在将晶片从晶片分离之前）密封的非硅基器件。 该装置包括要被保护的有源区域，接触区域和至少密封有效区域并使至少一部分接触区域暴露的光刻形成的结构。

    Microelectronic mechanical system and methods
    4.
    发明授权
    Microelectronic mechanical system and methods 有权
    微电子机械系统及方法

    公开(公告)号：US07183637B2

    公开(公告)日：2007-02-27

    申请号：US11129541

    申请日：2005-05-13

    申请人： Mike Bruner

    发明人： Mike Bruner

    IPC分类号： H01L21/00 ,  H01L21/461

    CPC分类号： B81C1/00484 ,  B81B2201/0271 ,  B81B2203/0136 ,  B81C1/00246 ,  B81C1/00333 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0136 ,  B81C2203/0735

    摘要： The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer, that preferably comprises silicon oxide and/or silicon nitride, and which is formed over an etch resistant substrate. A patterned device layer, preferably comprising silicon nitride, is embedded in a sacrificial material, preferably comprising polysilicon, and is disposed between the etch resistant substrate and the capping layer. Access trenches or holes are formed in to capping layer and the sacrificial material are selectively etched through the access trenches, such that portions of the device layer are release from sacrificial material. The etchant preferably comprises a noble gas fluoride NGF2x (wherein Ng=Xe, Kr or Ar: and where x=1, 2 or 3). After etching that sacrificial material, the access trenches are sealed to encapsulate released portions the device layer between the etch resistant substrate and the capping layer. The current invention is particularly useful for fabricating MEMS devices, multiple cavity devices and devices with multiple release features.

    摘要翻译： 本发明提供了包封的释放结构，其中间体及其制备方法。 多层结构具有覆盖层，其优选地包括氧化硅和/或氮化硅，并且其形成在耐蚀刻衬底上。 优选地包括氮化硅的图案化器件层嵌入牺牲材料中，优选地包括多晶硅，并且设置在耐蚀刻衬底和覆盖层之间。 进入沟槽或孔形成在覆盖层中，并且牺牲材料通过进入沟槽被选择性地蚀刻，使得器件层的部分从牺牲材料释放。 蚀刻剂优选包含惰性气体氟化物NGF 2X（其中Ng = Xe，Kr或Ar：其中x = 1,2或3）。 在蚀刻该牺牲材料之后，进入沟槽被密封以将器件层的释放部分封装在耐蚀刻衬底和覆盖层之间。 本发明对于制造具有多个释放特征的MEMS器件，多腔器件和器件特别有用。

    Microelectronic mechanical system and methods
    5.
    发明授权
    Microelectronic mechanical system and methods 有权
    微电子机械系统及方法

    公开(公告)号：US07049164B2

    公开(公告)日：2006-05-23

    申请号：US10268257

    申请日：2002-10-09

    申请人： Mike Bruner

    发明人： Mike Bruner

    IPC分类号： H01L21/00 ,  H01L21/461

    CPC分类号： B81C1/00484 ,  B81B2201/0271 ,  B81B2203/0136 ,  B81C1/00246 ,  B81C1/00333 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0136 ,  B81C2203/0735

    摘要： The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer, that preferably comprises silicon oxide and/or silicon nitride, and which is formed over an etch resistant substrate. A patterned device layer, preferably comprising silicon nitride, is embedded in a sacrificial material, preferably comprising polysilicon, and is disposed between the etch resistant substrate and the capping layer. Access trenches or holes are formed in to capping layer and the sacrificial material are selectively etched through the access trenches, such that portions of the device layer are release from sacrificial material. The etchant preferably comprises a noble gas fluoride NGF2x (wherein Ng=Xe, Kr or Ar: and where x=1, 2 or 3). After etching that sacrificial material, the access trenches are sealed to encapsulate released portions the device layer between the etch resistant substrate and the capping layer. The current invention is particularly useful for fabricating MEMS devices, multiple cavity devices and devices with multiple release features.

    摘要翻译： 本发明提供了包封的释放结构，其中间体及其制备方法。 多层结构具有覆盖层，其优选地包括氧化硅和/或氮化硅，并且其形成在耐蚀刻衬底上。 优选地包括氮化硅的图案化器件层嵌入牺牲材料中，优选地包括多晶硅，并且设置在耐蚀刻衬底和覆盖层之间。 进入沟槽或孔形成在覆盖层中，并且牺牲材料通过进入沟槽被选择性地蚀刻，使得器件层的部分从牺牲材料释放。 蚀刻剂优选包含惰性气体氟化物NGF 2X（其中Ng = Xe，Kr或Ar：其中x = 1,2或3）。 在蚀刻该牺牲材料之后，进入沟槽被密封以将器件层的释放部分封装在耐蚀刻衬底和覆盖层之间。 本发明对于制造具有多个释放特征的MEMS器件，多腔器件和器件特别有用。

    Microelectronic mechanical system and methods
    6.
    发明授权
    Microelectronic mechanical system and methods 有权
    微电子机械系统及方法

    公开(公告)号：US06991953B1

    公开(公告)日：2006-01-31

    申请号：US10112962

    申请日：2002-03-28

    申请人： Mike Bruner ,  Richard Yeh ,  Jim Hunter

    发明人： Mike Bruner ,  Richard Yeh ,  Jim Hunter

    IPC分类号： H01L21/308 ,  H01L21/469

    CPC分类号： B81C1/00484 ,  B81B2201/0271 ,  B81B2203/0136 ,  B81C1/00246 ,  B81C1/00333 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0136 ,  B81C2203/0735

    摘要： The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. A multi-layer structure has a capping layer, that preferably comprises silicon oxide and/or silicon nitride, and which is formed over an etch resistant substrate. A patterned device layer, preferably comprising silicon nitride, is embedded in a sacrificial material, preferably comprising poly-silicon, and is disposed between the etch resistant substrate and the capping layer. Access trenches or holes are formed in to capping layer and the sacrificial material is selectively etched through the access trenches, such that portions of the device layer are release from sacrificial material. The etchant preferably comprises a noble gas fluoride NGF2x, (wherein NG=Xe, Kr or Ar: and where x=1, 2 or 3). After etching that sacrificial material, the access trenches are sealed to encapsulate released portions the device layer between the etch resistant substrate and the capping layer. The current invention is particularly useful for fabricating MEMS devices, multiple cavity devices and devices with multiple release features.

    摘要翻译： 本发明提供了包封的释放结构，其中间体及其制备方法。 多层结构具有覆盖层，其优选地包括氧化硅和/或氮化硅，并且其形成在耐蚀刻衬底上。 优选地包括氮化硅的图案化器件层嵌入牺牲材料中，优选地包括多晶硅，并且设置在耐蚀刻衬底和覆盖层之间。 进入沟槽或孔形成在覆盖层中，并且牺牲材料被选择性地蚀刻通过进入沟槽，使得器件层的部分从牺牲材料释放。 蚀刻剂优选包含惰性气体氟化物NGF 2X（其中NG = Xe，Kr或Ar：其中x = 1,2或3）。 在蚀刻该牺牲材料之后，进入沟槽被密封以将器件层的释放部分封装在耐蚀刻衬底和覆盖层之间。 本发明对于制造具有多个释放特征的MEMS器件，多腔器件和器件特别有用。

    Microelectronic mechanical system and methods
    7.
    发明授权
    Microelectronic mechanical system and methods 有权
    微电子机械系统及方法

    公开(公告)号：US06930364B2

    公开(公告)日：2005-08-16

    申请号：US09952626

    申请日：2001-09-13

    申请人： Mike Bruner

    发明人： Mike Bruner

    IPC分类号： B81C1/00 ,  B81B3/00 ,  B81B7/00 ,  H01L21/46 ,  H02N1/00 ,  H03H9/24 ,  H01L27/14

    CPC分类号： B81C1/00484 ,  B81B2201/0271 ,  B81B2203/0136 ,  B81C1/00246 ,  B81C1/00333 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0136 ,  B81C2203/0735

    摘要： The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer, that preferably comprises silicon oxide and/or silicon nitride, and which is formed over an etch resistant substrate. A patterned device layer, preferably comprising silicon nitride, is embedded in a sacrificial material, preferably comprising polysilicon, and is disposed between the etch resistant substrate and the capping layer. Access trenches or holes are formed in to capping layer and the sacrificial material are selectively etched through the access trenches, such that portions of the device layer are release from sacrificial material. The etchant preferably comprises a noble gas fluoride NGF2x (wherein Ng=Xe, Kr or Ar: and where x=1, 2 or 3). After etching that sacrificial material, the access trenches are sealed to encapsulate released portions the device layer between the etch resistant substrate and the capping layer. The current invention is particularly useful for fabricating MEMS devices, multiple cavity devices and devices with multiple release features.

    摘要翻译： 本发明提供了包封的释放结构，其中间体及其制备方法。 多层结构具有覆盖层，其优选地包括氧化硅和/或氮化硅，并且其形成在耐蚀刻衬底上。 优选地包括氮化硅的图案化器件层嵌入牺牲材料中，优选地包括多晶硅，并且设置在耐蚀刻衬底和覆盖层之间。 进入沟槽或孔形成在覆盖层中，并且牺牲材料通过进入沟槽被选择性地蚀刻，使得器件层的部分从牺牲材料释放。 蚀刻剂优选包含惰性气体氟化物NGF 2X（其中Ng = Xe，Kr或Ar：其中x = 1,2或3）。 在蚀刻该牺牲材料之后，进入沟槽被密封以将器件层的释放部分封装在耐蚀刻衬底和覆盖层之间。 本发明对于制造具有多个释放特征的MEMS器件，多腔器件和器件特别有用。

    Microelectronic mechanical system and methods
    8.
    发明申请
    Microelectronic mechanical system and methods 有权

    公开(公告)号：US20050221528A1

    公开(公告)日：2005-10-06

    申请号：US11129541

    申请日：2005-05-13

    申请人： Mike Bruner

    发明人： Mike Bruner

    IPC分类号： B81C1/00 ,  B81B3/00 ,  B81B7/00 ,  H01L21/46 ,  H02N1/00 ,  H03H9/24

    CPC分类号： B81C1/00484 ,  B81B2201/0271 ,  B81B2203/0136 ,  B81C1/00246 ,  B81C1/00333 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0136 ,  B81C2203/0735

    摘要： The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer, that preferably comprises silicon oxide and/or silicon nitride, and which is formed over an etch resistant substrate. A patterned device layer, preferably comprising silicon nitride, is embedded in a sacrificial material, preferably comprising polysilicon, and is disposed between the etch resistant substrate and the capping layer. Access trenches or holes are formed in to capping layer and the sacrificial material are selectively etched through the access trenches, such that portions of the device layer are release from sacrificial material. The etchant preferably comprises a noble gas fluoride NGF2x (wherein Ng=Xe, Kr or Ar: and where x=1, 2 or 3). After etching that sacrificial material, the access trenches are sealed to encapsulate released portions the device layer between the etch resistant substrate and the capping layer. The current invention is particularly useful for fabricating MEMS devices, multiple cavity devices and devices with multiple release features.

    Wafer-level seal for non-silicon-based devices
    9.
    发明申请
    Wafer-level seal for non-silicon-based devices 有权
    非硅基器件的晶圆级密封

    公开(公告)号：US20050168103A1

    公开(公告)日：2005-08-04

    申请号：US11041857

    申请日：2005-01-24

    申请人： Gregory Miller ,  Mike Bruner

    发明人： Gregory Miller ,  Mike Bruner

    IPC分类号： B81B7/00 ,  H03H3/08 ,  H03H9/02 ,  H01L41/04 ,  H01L29/84 ,  H02N2/00 ,  H04R31/00

    CPC分类号： B81C1/00293 ,  B81C2203/0136 ,  H03H3/08 ,  H03H9/02921 ,  H03H9/02984 ,  H03H9/1092 ,  Y10T29/42 ,  Y10T29/49005 ,  Y10T29/49011 ,  Y10T29/4908 ,  Y10T29/49126

    摘要： One embodiment disclosed relates to a method for sealing an active area of a non-silicon-based device on a wafer. The method includes providing a sacrificial material over at least the active area of the non-silicon-based device, depositing a seal coating over the wafer so that the seal coating covers the sacrificial material, and replacing the sacrificial material with a target atmosphere. Another embodiment disclosed relates to a non-silicon-based device sealed at the wafer level (i.e. prior to separation of the die from the wafer). The device includes an active area to be protected, a contact area, and a lithographically-formed structure sealing at least the active area and leaving at least a portion of the contact area exposed.

    摘要翻译： 公开的一个实施例涉及一种用于密封晶片上的非硅基器件的有源区域的方法。 该方法包括在非硅基器件的至少有源区域上提供牺牲材料，在晶片上沉积密封涂层，使得密封涂层覆盖牺牲材料，并用目标气氛代替牺牲材料。 所公开的另一实施例涉及在晶片级（即，在将晶片从晶片分离之前）密封的非硅基器件。 该装置包括要被保护的有源区域，接触区域和至少密封有效区域并使至少一部分接触区域暴露的光刻形成的结构。