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公开(公告)号:US20170084712A1
公开(公告)日:2017-03-23
申请号:US15179393
申请日:2016-06-10
IPC: H01L29/49 , H01L29/66 , H01L21/8238
CPC classification number: H01L29/4983 , H01L21/0214 , H01L21/02167 , H01L21/0217 , H01L21/0332 , H01L21/31053 , H01L21/31116 , H01L21/31144 , H01L21/76205 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L21/823481 , H01L21/823814 , H01L21/823821 , H01L21/823842 , H01L21/823864 , H01L27/0886 , H01L29/0649 , H01L29/42368 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66795
Abstract: A method of filling trenches between gates includes forming a first and a second dummy gate over a substrate, the first and second dummy gates including a sacrificial gate material and a hard mask layer; forming a first gate spacer along a sidewall of the first dummy gate and a second gate spacer along a sidewall of the second dummy gate; performing an epitaxial growth process to form a source/drain on the substrate between the first and second dummy gates; disposing a conformal liner over the first and second dummy gates and the source/drain; disposing an oxide on the conformal liner between the first and second dummy gates; recessing the oxide to a level below the hard mask layers of the first and second dummy gates to form a recessed oxide; and depositing a spacer material over the recessed oxide between the first dummy gate and the second dummy gate.
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公开(公告)号:US09601335B2
公开(公告)日:2017-03-21
申请号:US15282836
申请日:2016-09-30
Inventor: Andrew M. Greene , Ryan O. Jung , Ruilong Xie , Peng Xu
IPC: H01L21/28 , H01L23/60 , H01L21/84 , H01L21/8238 , H01L29/423 , H01L27/092 , H01L29/08 , H01L29/06 , H01L27/12
CPC classification number: H01L21/76224 , H01L21/0217 , H01L21/28114 , H01L21/28123 , H01L21/32139 , H01L21/823437 , H01L21/823481 , H01L21/823814 , H01L21/823821 , H01L23/60 , H01L27/088 , H01L27/0924 , H01L27/1211 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/42368 , H01L29/42376 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/78
Abstract: A method for forming a gate cut region includes forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a substrate, forming a dummy gate dielectric and a dummy gate conductor in the trench and planarizing a top surface to reach the hard mask. The dummy gate conductor is patterned to form a cut trench in a cut region. The dummy gate conductor is recessed, and the cut trench is filled with a first dielectric material. The dummy layer is removed and spacers are formed. A gate line is opened up and the dummy gate conductor is removed from the gate line trench. A gate dielectric and conductor are deposited, and a gate cap layer provides a second dielectric that is coupled to the first dielectric material in the cut trench to form a cut last structure.
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公开(公告)号:US20160380078A1
公开(公告)日:2016-12-29
申请号:US15092272
申请日:2016-04-06
Inventor: Huiming Bu , Andrew M. Greene , Balasubramanian Pranatharthiharan , Ruilong Xie
IPC: H01L29/66 , H01L27/088
CPC classification number: H01L21/823475 , H01L21/02167 , H01L21/0217 , H01L21/02274 , H01L21/31111 , H01L21/32139 , H01L21/76802 , H01L21/76837 , H01L21/823418 , H01L21/823425 , H01L21/823431 , H01L21/823437 , H01L27/088 , H01L29/41783 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66636 , H01L29/66795
Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.
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