公开(公告)号：US09536793B1

公开(公告)日：2017-01-03

申请号：US15135917

申请日：2016-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Kwan-Yong Lim ,  Steven John Bentley ,  Chanro Park

IPC: H01L29/786 ,  H01L21/8238

CPC classification number: H01L21/823828 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823885

Abstract: Methods for self-aligned gate-first VFETs using gate-spacer recess and the resulting devices are disclosed. Embodiments include providing a substrate including adjacent transistor regions; forming adjacent and spaced fin-structures each including hardmask over a fin and over a different transistor region; forming a gate-dielectric and metal-spacer consecutively on each side of each fin-structure; forming a liner on all exposed surfaces of the hardmask, gate-dielectrics, and metal-spacers and the substrate; forming an ILD filling spaces between the fin-structures and coplanar with an upper surface of the liner; removing the liner over the fin-structures; removing the hardmask and recessing the liner, the gate-dielectrics and metal-spacers of each fin-structure creating cavities in the ILD; forming a low-k spacer on sidewalls of and over the metal-spacers and liners in each cavity; forming a top S/D structure over the gate-dielectric and fin in each cavity; and forming a top S/D contact over each top S/D structure.

Abstract translation: 公开了使用栅极 - 间隔物凹槽的自对准栅极 - 第一VFET和所得到的器件的方法。 实施例包括提供包括相邻晶体管区域的衬底; 形成相邻和间隔的翅片结构，每个翅片结构包括翅片上的硬掩模和不同的晶体管区域上的硬掩模; 在每个翅片结构的每一侧上连续形成栅电介质和金属间隔物; 在硬掩模，栅极 - 电介质和金属间隔物和基底的所有暴露表面上形成衬垫; 在翅片结构之间形成ILD填充空间并与衬套的上表面共面; 将衬垫移出翅片结构; 去除硬掩模并使衬垫凹陷，每个鳍结构的栅电介质和金属间隔件在ILD中产生空腔; 在每个腔中的金属间隔件和衬垫的侧壁上形成低k间隔物; 在每个腔中的栅电介质和鳍上形成顶部S / D结构; 并且在每个顶部S / D结构上形成顶部S / D接触。

公开(公告)号：US20160163604A1

公开(公告)日：2016-06-09

申请号：US14674924

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Ryan Ryoung-Han Kim ,  Kwan-Yong Lim ,  Chanro Park

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/823878 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes forming first sacrificial gate structures above a fin for two active gates and a dummy gate, removing the first sacrificial gate structure for the dummy gate so as to define a cavity that exposes the fin while leaving the first sacrificial gate structures for the two active gates intact, etching through the cavity to form a trench in the fin under the cavity, forming a second sacrificial gate structure for the dummy gate, removing the first sacrificial gate structures for the two active gates and the second sacrificial gate structure for the dummy gate so as to define a replacement gate cavity for the two active gates and the dummy gate, and forming a replacement gate structure in each of the replacement gate cavities, wherein the replacement gate structure for the dummy gate extends into the trench in the fin.

Abstract translation: 本文公开的一种说明性方法包括在两个有源栅极和伪栅极的鳍片的上方形成第一牺牲栅极结构，去除用于伪栅极的第一牺牲栅极结构，以便限定在离开第一牺牲栅极结构的同时露出鳍片的空腔 对于完整的两个有源栅极，蚀刻通过空腔以在腔下方的鳍形成沟槽，形成用于伪栅极的第二牺牲栅极结构，去除用于两个有源栅极和第二牺牲栅极结构的第一牺牲栅极结构 为了形成用于两个有源栅极和虚拟栅极的替代栅极腔，并且在每个替代栅极腔中形成替代栅极结构，其中用于伪栅极的替代栅极结构延伸到沟槽中 翅膀

公开(公告)号：US09362181B1

公开(公告)日：2016-06-07

申请号：US14674924

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Ryan Ryoung-Han Kim ,  Kwan-Yong Lim ,  Chanro Park

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L21/823878 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes forming first sacrificial gate structures above a fin for two active gates and a dummy gate, removing the first sacrificial gate structure for the dummy gate so as to define a cavity that exposes the fin while leaving the first sacrificial gate structures for the two active gates intact, etching through the cavity to form a trench in the fin under the cavity, forming a second sacrificial gate structure for the dummy gate, removing the first sacrificial gate structures for the two active gates and the second sacrificial gate structure for the dummy gate so as to define a replacement gate cavity for the two active gates and the dummy gate, and forming a replacement gate structure in each of the replacement gate cavities, wherein the replacement gate structure for the dummy gate extends into the trench in the fin.

Abstract translation: 本文公开的一种说明性方法包括在两个有源栅极和伪栅极的鳍片的上方形成第一牺牲栅极结构，去除用于伪栅极的第一牺牲栅极结构，以便限定在离开第一牺牲栅极结构的同时露出鳍片的空腔 对于完整的两个有源栅极，蚀刻通过空腔以在腔下方的鳍形成沟槽，形成用于伪栅极的第二牺牲栅极结构，去除用于两个有源栅极和第二牺牲栅极结构的第一牺牲栅极结构 为了形成用于两个有源栅极和虚拟栅极的替代栅极腔，并且在每个替代栅极腔中形成替代栅极结构，其中用于伪栅极的替代栅极结构延伸到沟槽中 翅膀

公开(公告)号：US09324799B2

公开(公告)日：2016-04-26

申请号：US14480974

申请日：2014-09-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Kwan-Yong Lim ,  Sukwon Hong

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/66 ,  H01L21/762 ,  H01L29/36 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L29/7856 ,  H01L21/2253 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/7851

Abstract: Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof.

Abstract translation: 提供了制造包括FinFET结构的电路结构的方法，包括：提供衬底和在衬底上方具有第一阈值电压的第一材料以及具有低于第一材料之上的第一阈值电压的第二阈值电压的第二材料; 形成具有由所述第一材料形成的基部翅片部分和由所述第二材料形成的上部翅片部分的翅片; 在所述翅片上提供栅极结构以形成一个或多个FinFET结构，其中所述栅极结构至少缠绕在所述上鳍部分上并具有低于所述第一阈值电压并高于所述第二阈值电压的工作电压，使得所述上翅片 部分限定一个或多个FinFET结构的通道尺寸。 还提供了包括FinFET结构的电路结构，其中FinFET结构具有仅由其上翅部分限定的均匀通道尺寸。