公开(公告)号：US09799751B1

公开(公告)日：2017-10-24

申请号：US15132383

申请日：2016-04-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Steven J. Bentley ,  Kwan-Yong Lim

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L21/321 ,  H01L21/265 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L29/66666 ,  H01L21/02164 ,  H01L21/26513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823885 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: One illustrative method disclosed herein includes forming a multi-layered sidewall spacer (MLSS) around a vertically oriented channel semiconductor structure, wherein the MLSS comprises a non-sacrificial innermost first spacer (a high-k insulating material), a sacrificial outermost spacer and at least one non-sacrificial second spacer (a metal-containing material) positioned between the innermost spacer and the outermost spacer, removing at least a portion of the sacrificial outermost spacer from the MLSS while leaving the at least one non-sacrificial second spacer and the non-sacrificial innermost first spacer in position and forming a final conductive gate electrode in place of the removed sacrificial outermost spacer.

公开(公告)号：US09607893B1

公开(公告)日：2017-03-28

申请号：US15202949

申请日：2016-07-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： John H. Zhang ,  Carl J. Radens ,  Lawrence A. Clevenger

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816

Abstract: Disclosed are embodiments of a method, wherein metal lines and vias of an integrated circuit IC) metal level of are formed without requiring separate cut masks to pattern the trenches for the metal lines and the via holes for the vias. Trenches are formed in an upper portion of a dielectric layer. Each trench is filled with a sacrificial material. A mask is formed above the dielectric layer and patterned with one or more openings, each opening exposing one or more segments of the sacrificial material in one or more of the trenches, respectively. A sidewall spacer is formed in each opening and a selective etch process is performed to form one or more via holes that extend through the sacrificial material and through the lower portion of the dielectric layer below. Subsequently, all the sacrificial material is removed and metal is deposited, thereby forming self-aligned metal lines and via(s).

公开(公告)号：US09530863B1

公开(公告)日：2016-12-27

申请号：US15097574

申请日：2016-04-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Carl Radens ,  Steven J. Bentley ,  Brian A. Cohen ,  Kwan-Yong Lim

IPC: H01L21/306 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L29/0847 ,  H01L29/66666 ,  H01L29/7827

Abstract: One illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure, forming a layer of a bottom spacer material around the vertically oriented channel semiconductor structure and forming a sacrificial material layer above the layer of a bottom spacer material. In this example, the method further includes forming a sidewall spacer adjacent the vertically oriented channel semiconductor structure and above an upper surface of the sacrificial material layer, removing the sacrificial material layer so as to define a replacement gate cavity between a bottom surface of the sidewall spacer and the layer of a bottom spacer material, and forming a replacement gate structure in the replacement gate cavity.

Abstract translation: 本文中公开的一种说明性方法包括形成垂直取向的沟道半导体结构，在垂直取向的沟道半导体结构周围形成底部间隔物材料的层，并在底部间隔物材料的层的上方形成牺牲材料层。 在该示例中，该方法还包括形成邻近垂直取向的沟道半导体结构并且在牺牲材料层的上表面上方的侧壁间隔物，去除牺牲材料层，以便在侧壁的底表面之间限定替换栅腔 间隔物和底部间隔物材料的层，并且在替换浇口腔中形成替代浇口结构。

公开(公告)号：US10510613B2

公开(公告)日：2019-12-17

申请号：US15878081

申请日：2018-01-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Xusheng Wu ,  Haigou Huang ,  John H. Zhang ,  Pei Liu ,  Laertis Economikos

IPC: H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L23/535 ,  H01L21/28

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a contact over an active gate structure and methods of manufacture. The structure includes: an active gate structure composed of conductive material located between sidewall material; an upper sidewall material above the sidewall material, the upper sidewall material being different material than the sidewall material; and a contact structure in electrical contact with the conductive material of the active gate structure. The contact structure is located between the sidewall material and between the upper sidewall material.

公开(公告)号：US20180114850A1

公开(公告)日：2018-04-26

申请号：US15840835

申请日：2017-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/66666 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7827 ,  H01L29/78642

Abstract: A vertical transistor device includes a vertically oriented channel semiconductor structure, a bottom source/drain (S/D) region, a top source/drain (S/D) region, and a gate structure positioned around the vertically oriented channel semiconductor structure, above the bottom source/drain (S/D) region, and below the top source/drain (S/D) region. The gate structure includes a gate electrode and a gate insulation layer positioned between the gate electrode and at least a portion of the vertically oriented channel semiconductor structure. A top spacer is positioned between the gate electrode and at least a portion of the top source/drain (S/D) region, a bottom spacer is positioned between the gate electrode and at least a portion of the bottom source/drain (S/D) region, and a gate cap is positioned around an outer perimeter surface of the gate structure, wherein the top spacer, the bottom spacer, and the gate cap all include a same insulating material.

公开(公告)号：US09865543B1

公开(公告)日：2018-01-09

申请号：US15416152

申请日：2017-01-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qiang Fang ,  Haigou Huang ,  Stan Tsai ,  John H. Zhang ,  Xingzhao Shi ,  Tai Fong Chao

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/82 ,  H01L23/528 ,  H01L21/321 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L23/5283 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/53209

Abstract: A process for forming a conductive structure includes the formation of a self-aligned, inlaid conductive cap over a cobalt-based contact. The inlaid conductive cap is formed using a damascene process by depositing a conductive layer comprising tungsten or copper over a recessed cobalt-based contact, followed by a CMP step to remove excess portions of the conductive layer. The conductive cap can cooperate with a liner/barrier layer to form an effective barrier to cobalt migration and oxidation.

公开(公告)号：US09536793B1

公开(公告)日：2017-01-03

申请号：US15135917

申请日：2016-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Kwan-Yong Lim ,  Steven John Bentley ,  Chanro Park

IPC: H01L29/786 ,  H01L21/8238

CPC classification number: H01L21/823828 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823885

Abstract: Methods for self-aligned gate-first VFETs using gate-spacer recess and the resulting devices are disclosed. Embodiments include providing a substrate including adjacent transistor regions; forming adjacent and spaced fin-structures each including hardmask over a fin and over a different transistor region; forming a gate-dielectric and metal-spacer consecutively on each side of each fin-structure; forming a liner on all exposed surfaces of the hardmask, gate-dielectrics, and metal-spacers and the substrate; forming an ILD filling spaces between the fin-structures and coplanar with an upper surface of the liner; removing the liner over the fin-structures; removing the hardmask and recessing the liner, the gate-dielectrics and metal-spacers of each fin-structure creating cavities in the ILD; forming a low-k spacer on sidewalls of and over the metal-spacers and liners in each cavity; forming a top S/D structure over the gate-dielectric and fin in each cavity; and forming a top S/D contact over each top S/D structure.

Abstract translation: 公开了使用栅极 - 间隔物凹槽的自对准栅极 - 第一VFET和所得到的器件的方法。 实施例包括提供包括相邻晶体管区域的衬底; 形成相邻和间隔的翅片结构，每个翅片结构包括翅片上的硬掩模和不同的晶体管区域上的硬掩模; 在每个翅片结构的每一侧上连续形成栅电介质和金属间隔物; 在硬掩模，栅极 - 电介质和金属间隔物和基底的所有暴露表面上形成衬垫; 在翅片结构之间形成ILD填充空间并与衬套的上表面共面; 将衬垫移出翅片结构; 去除硬掩模并使衬垫凹陷，每个鳍结构的栅电介质和金属间隔件在ILD中产生空腔; 在每个腔中的金属间隔件和衬垫的侧壁上形成低k间隔物; 在每个腔中的栅电介质和鳍上形成顶部S / D结构; 并且在每个顶部S / D结构上形成顶部S / D接触。

公开(公告)号：US10115633B2

公开(公告)日：2018-10-30

申请号：US15653127

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Carl J. Radens ,  Lawrence A. Clevenger

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768

Abstract: A method for producing self-aligned line end vias and the resulting device are provided. Embodiments include trench lines formed in a dielectric layer; each trench line including a pair of self aligned line end vias; and a high-density plasma (HDP) oxide, silicon carbide (SiC) or silicon carbon nitride (SiCNH) formed between each pair of self aligned line end vias, wherein the trench lines and self aligned line end vias are filled with a metal liner and metal.

公开(公告)号：US09882025B1

公开(公告)日：2018-01-30

申请号：US15281227

申请日：2016-09-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang

IPC: H01L21/48 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/66666 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: One illustrative method disclosed herein includes, among other things, forming a gate structure around a vertically oriented channel semiconductor structure above a bottom source/drain (S/D) region and below a top source/drain (S/D) region, the gate structure comprising a gate electrode and a gate insulation layer, a first portion of the gate insulation layer being positioned between the gate electrode and the vertically oriented channel semiconductor structure, removing second portion and third portions of the gate insulation layer while leaving at least some of the first portion in position to define a top spacer recess and a lower spacer recess and performing a common deposition process to simultaneously form a top spacer in the top spacer recess and a lower spacer in the lower spacer recess.

公开(公告)号：US09761491B1

公开(公告)日：2017-09-12

申请号：US15370404

申请日：2016-12-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Xusheng Wu ,  John H. Zhang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/088 ,  H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L23/535

CPC classification number: H01L21/76897 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/78642 ,  Y02E10/50

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a self-aligned deep contact for a vertical field effect transistor (VFET) and methods of manufacture. The structure includes a plurality of fin structures, a first contact landing on a substrate material between a first set of fin structures of the plurality of fin structures, sidewalls of the first contact being in direct contact with an insulator material of the first set of the fin structures, and a second contact landing on a work function material between a second set of fin structures of the plurality of fin structures, sidewalls of the second contact being in direct contact with the insulator material of the second set of the fin structures.