公开(公告)号：US08097542B2

公开(公告)日：2012-01-17

申请号：US12260147

申请日：2008-10-29

申请人： Karsten Wieczorek ,  Manfred Horstmann ,  Peter Huebler ,  Kerstin Ruttloff

发明人： Karsten Wieczorek ,  Manfred Horstmann ,  Peter Huebler ,  Kerstin Ruttloff

IPC分类号： H01L21/31

CPC分类号： H01L21/76826 ,  H01L21/76832 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L29/7843 ,  Y02P80/30

摘要： In a dual stress liner approach, an intermediate etch stop material may be provided on the basis of a plasma-assisted oxidation process rather than by deposition so the corresponding thickness of the etch stop material may be reduced. Consequently, the resulting aspect ratio may be less pronounced compared to conventional strategies, thereby reducing deposition-related irregularities which may translate into a significant reduction of yield loss, in particular for highly scaled semiconductor devices.

摘要翻译： 在双重应力衬垫方法中，可以基于等离子体辅助氧化工艺而不是通过沉积来提供中间蚀刻停止材料，从而减小蚀刻停止材料的对应厚度。 因此，与常规策略相比，所产生的纵横比可能不太明显，从而减少沉积相关的不规则性，这可能转化为产量损失的显着降低，特别是对于高度缩放的半导体器件。

公开(公告)号：US20100025776A1

公开(公告)日：2010-02-04

申请号：US12472969

申请日：2009-05-27

申请人： Manfred Horstmann ,  Patrick Press ,  Karsten Wieczorek ,  Kerstin Ruttloff

发明人： Manfred Horstmann ,  Patrick Press ,  Karsten Wieczorek ,  Kerstin Ruttloff

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L21/823462 ,  H01L21/28035 ,  H01L21/823456 ,  H01L27/11 ,  H01L29/4238 ,  H01L29/513

摘要： In a memory cell, the drive current capabilities of the transistors may be adjusted by locally providing an increased gate dielectric thickness and/or gate length of one or more of the transistors of the memory cell. That is, the gate length and/or the gate dielectric thickness may vary along the transistor width direction, thereby providing an efficient mechanism for adjusting the effective drive current capability while at the same time allowing the usage of a simplified geometry of the active region, which may result in enhanced production yield due to enhanced process uniformity. In particular, the probability of creating short circuits caused by nickel silicide portions may be reduced.

摘要翻译： 在存储器单元中，晶体管的驱动电流能力可以通过局部地提供存储单元的一个或多个晶体管的增加的栅介质厚度和/或栅极长度来调节。 也就是说，栅极长度和/或栅极电介质厚度可以沿晶体管宽度方向变化，从而提供用于调节有效驱动电流能力的有效机构，同时允许使用有源区域的简化几何形状， 这可能由于增加的工艺均匀性而导致产量提高。 特别地，可能减少由硅化镍部分引起的产生短路的可能性。

公开(公告)号：US20090273036A1

公开(公告)日：2009-11-05

申请号：US12397574

申请日：2009-03-04

申请人： Manfred Horstmann ,  Peter Javorka ,  Karsten Wieczorek ,  Kerstin Ruttloff

发明人： Manfred Horstmann ,  Peter Javorka ,  Karsten Wieczorek ,  Kerstin Ruttloff

IPC分类号： H01L27/092 ,  H01L21/4763

CPC分类号： H01L21/823842 ,  H01L21/823871

摘要： By incorporating nitrogen into the P-doped regions and N-doped regions of the gate electrode material prior to patterning the gate electrode structure, yield losses due to reactive wet chemical cleaning processes may be significantly reduced.

摘要翻译： 通过在对栅电极结构进行构图之前将氮掺入P掺杂区域和栅极电极材料的N掺杂区域中，可以显着降低由于反应性湿化学清洗过程引起的屈服损失。

公开(公告)号：US20050037548A1

公开(公告)日：2005-02-17

申请号：US10949089

申请日：2004-09-24

申请人： Karsten Wieczorek ,  Manfred Horstmann ,  Christian Krueger

发明人： Karsten Wieczorek ,  Manfred Horstmann ,  Christian Krueger

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L29/78696 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78684

摘要： An SOI transistor element and a method of fabricating the same is disclosed, wherein a high concentration of stationary point defects is created by including a region within the active transistor area that has a slight lattice mismatch. In one particular embodiment, a silicon germanium layer is provided in the active area having a high concentration of point defects due to relaxing the strain of the silicon germanium layer upon heat treating the transistor element. Due to the point defects, the recombination rate is significantly increased, thereby reducing the number of charged carriers stored in the active area.

摘要翻译： 公开了SOI晶体管元件及其制造方法，其中通过在有源晶体管区域内包含具有轻微晶格失配的区域来产生高浓度的固定点缺陷。 在一个特定实施例中，由于在对晶体管元件进行热处理时放松硅锗层的应变，在有源区域中提供了具有高浓度点缺陷的硅锗层。 由于点缺陷，复合率显着增加，从而减少存储在有源区域中的带电载流子数量。

公开(公告)号：US06491799B1

公开(公告)日：2002-12-10

申请号：US09766738

申请日：2001-01-22

申请人： Frederick N. Hause ,  Karsten Wieczorek ,  Manfred Horstmann

发明人： Frederick N. Hause ,  Karsten Wieczorek ,  Manfred Horstmann

IPC分类号： C23C1434

CPC分类号： C23C14/10 ,  C23C14/3407 ,  C23C14/3471

摘要： The method disclosed herein comprises initially providing a tool comprised of a process chamber, a lid above the process chamber, an RF coil for assisting in generating a plasma in the chamber, a substrate support, and a power supply coupled to the substrate support. The method continues with the step of positioning a substrate in the tool adjacent the substrate support, introducing a noble gas into the chamber, and forming a layer of material above the substrate by sputtering the lid material by performing at least the following steps: applying approximately 200-300 watts of power to the RF coil at a frequency of approximately 400 KHz and applying approximately 20-60 watts of power to the substrate at a frequency of approximately 13.56 MHz.

摘要翻译： 本文公开的方法包括最初提供一种工具，其包括处理室，处理室上方的盖，用于辅助在室中产生等离子体的RF线圈，衬底支撑件和耦合到衬底支撑件的电源。 该方法继续以下步骤：将衬底定位在邻近衬底支撑件的工具中，将惰性气体引入腔室中，以及通过至少执行以下步骤溅射盖材料在衬底上方形成材料层：近似施加 以大约400KHz的频率向RF线圈施加200-300瓦的功率，并以大约13.56MHz的频率向衬底施加大约20-60瓦的功率。

公开(公告)号：US06218250B1

公开(公告)日：2001-04-17

申请号：US09324183

申请日：1999-06-02

申请人： Frederick N. Hause ,  Karsten Wieczorek ,  Manfred Horstmann

发明人： Frederick N. Hause ,  Karsten Wieczorek ,  Manfred Horstmann

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28518 ,  H01L29/456 ,  H01L29/4933

摘要： A semiconductor device includes a substrate, a gate structure, a plurality of sidewall spacers, and a plurality of first silicide layers. The gate structure is positioned above the substrate. The plurality of sidewall spacers are positioned adjacent to the gate structure. The first silicide layers are positioned in the substrate and have first ends that extend underneath the sidewall spacers. A method for forming a semiconductor device includes forming a gate structure above a substrate. A plurality of sidewall spacers are formed adjacent the gate structure. An implant material is disposed into the substrate using a tilted implantation process that is adapted to form first implant regions in the substrate. The implant regions have first ends that extend underneath the sidewall spacers by a first distance.

摘要翻译： 半导体器件包括衬底，栅极结构，多个侧壁间隔物和多个第一硅化物层。 栅极结构位于衬底上方。 多个侧壁间隔件邻近门结构定位。 第一硅化物层位于衬底中并且具有在侧壁间隔物下方延伸的第一端。 一种形成半导体器件的方法包括在衬底上形成栅极结构。 在栅极结构附近形成多个侧壁间隔物。 使用倾斜的注入工艺将注入材料设置到衬底中，所述倾斜注入工艺适于在衬底中形成第一注入区域。 植入区域具有在侧壁间隔物下方延伸第一距离的第一端。

公开(公告)号：US6133124A

公开(公告)日：2000-10-17

申请号：US245951

申请日：1999-02-05

申请人： Manfred Horstmann ,  Karsten Wieczorek ,  Frederick N. Hause

发明人： Manfred Horstmann ,  Karsten Wieczorek ,  Frederick N. Hause

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/425 ,  H01L21/44

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

摘要： Various methods of fabricating a silicide layer, and devices incorporating the same are provided. In one aspect, a method of fabricating a silicide layer on a substrate is provided. The method includes the steps of damaging the crystal structure of a portion of the substrate positioned beneath the spacer and depositing a layer of metal on the substrate. The metal layer and the substrate are heated to react the metal with the substrate and form the silicide layer, whereby a portion of the silicide layer extends laterally beneath the spacer. Any unreacted metal is removed. The method enables fabrication of silicide layers with substantial lateral encroachment into LDD structures, resulting in lower possible source-to-drain resistance and enhanced performance for transistors.

摘要翻译： 提供了制造硅化物层的各种方法，以及包含其的装置。 一方面，提供了在基板上制造硅化物层的方法。 该方法包括以下步骤：损坏位于间隔物下方的衬底的一部分的晶体结构并在衬底上沉积金属层。 加热金属层和衬底以使金属与衬底反应并形成硅化物层，由此硅化物层的一部分横向延伸在衬垫下方。 任何未反应的金属被去除。 该方法能够制造具有大量横向侵入LDD结构的硅化物层，导致晶体管的可能的源极 - 漏极电阻和增强的性能。

公开(公告)号：US20100203698A1

公开(公告)日：2010-08-12

申请号：US12763324

申请日：2010-04-20

申请人： Frank Wirbeleit ,  Rolf Stephan ,  Manfred Horstmann

发明人： Frank Wirbeleit ,  Rolf Stephan ,  Manfred Horstmann

IPC分类号： H01L21/336

CPC分类号： H01L21/28123 ,  H01L29/66545 ,  H01L29/6659

摘要： A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate.

摘要翻译： 形成半导体结构的方法包括提供半导体衬底。 在衬底上形成特征。 该特征在横向方向上基本上是均匀的。 执行适于将第一掺杂剂离子引入邻近该特征的衬底的至少一部分中的第一离子注入工艺。 横向的特征长度减小。 在特征的长度减小之后，执行适于将第二掺杂剂离子引入邻近该特征的衬底的至少一部分中的第二离子注入工艺。 该特征可以是要形成在半导体衬底上的场效应晶体管的栅电极。

公开(公告)号：US07629211B2

公开(公告)日：2009-12-08

申请号：US11684211

申请日：2007-03-09

申请人： Sven Beyer ,  Thorsten Kammler ,  Rolf Stephan ,  Manfred Horstmann

发明人： Sven Beyer ,  Thorsten Kammler ,  Rolf Stephan ,  Manfred Horstmann

IPC分类号： H01L21/331 ,  H01L21/8234

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

摘要： A method of forming a field effect transistor comprises providing a semiconductor substrate, a gate electrode being formed over the semiconductor substrate. At least one cavity is formed adjacent the gate electrode. A strain-creating element is formed in the at least one cavity. The strain-creating element comprises a compound material comprising a first chemical element and a second chemical element. A first concentration ratio between a concentration of the first chemical element in a first portion of the strain-creating element and a concentration of the second chemical element in the first portion of the strain-creating element is different from a second concentration ratio between a concentration of the first chemical element in a second portion of the strain-creating element and a concentration of the second chemical element in the second strain-creating element.

摘要翻译： 形成场效应晶体管的方法包括提供半导体衬底，栅电极形成在半导体衬底上。 在栅电极附近形成至少一个空腔。 应变产生元件形成在至少一个空腔中。 应变产生元件包括包含第一化学元素和第二化学元素的复合材料。 应变产生元件的第一部分中的第一化学元素的浓度与应变产生元件的第一部分中的第二化学元素的浓度之间的第一浓度比不同于第二浓度比， 的应变产生元件的第二部分中的第一化学元素和第二应变产生元件中的第二化学元素的浓度。

公开(公告)号：US20080268625A1

公开(公告)日：2008-10-30

申请号：US12023743

申请日：2008-01-31

申请人： Thomas Feudel ,  Rolf Stephan ,  Manfred Horstmann

发明人： Thomas Feudel ,  Rolf Stephan ,  Manfred Horstmann

IPC分类号： H01L21/425

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848

摘要： By combining an anneal process for adjusting the effective channel length and a substantially diffusion-free anneal process performed after a deep drain and source implantation, the vertical extension of the drain and source region may be increased substantially without affecting the previously adjusted channel length. In this manner, in SOI devices, the drain and source regions may extend down to the buried insulating layer, thereby reducing the parasitic capacitance, while the degree of dopant activation and thus series resistance in the extension regions may be improved. Furthermore, less critical process parameters during the anneal process for adjusting the channel length may provide the potential for reducing the lateral dimensions of the transistor devices.

摘要翻译： 通过组合用于调节有效沟道长度的退火工艺和在深漏极和源极注入之后执行的基本上无扩散的退火工艺，可以基本上增加漏极和源极区域的垂直延伸，而不影响先前调节的沟道长度。 以这种方式，在SOI器件中，漏极和源极区域可以向下延伸到掩埋绝缘层，从而减小寄生电容，同时可以改善延伸区域中的掺杂剂激活程度和因此的串联电阻。 此外，在用于调整沟道长度的退火工艺期间较不重要的工艺参数可以为降低晶体管器件的横向尺寸提供潜力。