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公开(公告)号:US20170317680A1
公开(公告)日:2017-11-02
申请号:US15520698
申请日:2014-10-30
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Ning Ge , Boon Bing Ng , Leong Yap Chia
IPC: H03K19/18 , H03K19/0944
CPC classification number: H03K19/18 , G11C13/0002 , H03K3/45 , H03K19/0944 , H03K19/173
Abstract: A device having ratioed logic with a high impedance load is described. The device includes a pull-down network coupled between a first voltage and an output. The device also includes a high impedance load coupled between a second voltage and the output. The high impedance load being smaller than a transistor of the pull-down network.
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公开(公告)号:US20170313093A1
公开(公告)日:2017-11-02
申请号:US15520338
申请日:2014-10-30
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Alexander Govyadinov , Adam L Ghozeil , Boon Bing Ng , Patrick Leonard , Raymond Connolly
CPC classification number: B41J2/17566 , B41J2/04541 , B41J2/0458 , B41J2/1404 , B41J2/14072 , B41J2/14153 , B41J2/175 , B41J2/18 , B41J2002/14467 , B41J2202/11 , B41J2202/12
Abstract: A print head has an ink slot and a sensing chamber having a first port connected to the fluid slot and a second port. The sensing chamber contains an ink level sensor. A recirculation passage extends from the fluid slot and is fluidly coupled to the second port. A fluid pump circulates fluid through the recirculation passage.
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公开(公告)号:US20170225462A1
公开(公告)日:2017-08-10
申请号:US15502588
申请日:2014-08-18
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Boon Bing Ng , Thida Ma Win , Jose Jehrome Rando
IPC: B41J2/14 , H01L23/522 , H01L23/00 , H01L23/528
CPC classification number: B41J2/14072 , H01L23/5226 , H01L23/5286 , H01L24/06
Abstract: In an example implementation, a grounding structure includes a perimeter ground line around the perimeter of a printhead die, and having north, south, east, and west segments. The structure includes an inter-slot ground line extending from the north segment to the south segment between two fluid slots, and an alternative ground line extending from the east segment to the west segment and intersecting the inter-slot ground line in a connection area near ends of the fluid slots.
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公开(公告)号:US11999162B2
公开(公告)日:2024-06-04
申请号:US17847754
申请日:2022-06-23
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Boon Bing Ng
CPC classification number: B41J2/04541 , B41J2/17546 , B41J2202/13 , B41J2202/17
Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a plurality of first data lines, a second data line, a first memory element, and a second memory element. The first memory element is enabled in response to first data on the plurality of first data lines. The second memory element is enabled in response to second data on the second data line.
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公开(公告)号:US20230382105A1
公开(公告)日:2023-11-30
申请号:US18448794
申请日:2023-08-11
Applicant: Hewlett-Packard Development Company, L.P.
Inventor: Boon Bing Ng , James Michael Gardner , Scott A. Linn
CPC classification number: B41J2/04536 , B41J2/04586 , G06F3/1293 , B41J2/04541 , B41J2/04555 , B41J2/04563 , B41J2/0458 , G06F13/1668 , G11C7/1069 , G11C16/10
Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component. The memory circuit includes a controllable selector connected in line with one of the signal paths via the I/O pads, the selector controllable to disconnect the corresponding signal path to the print component, and a memory component to store memory values associated with the print component. A control circuit, in response to a sequence of operating signals received by the I/O pads representing a memory read, to operate the controllable selector to disconnect the signal path to the print component to block the memory read of the print component, and provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.
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公开(公告)号:US11780222B2
公开(公告)日:2023-10-10
申请号:US17961476
申请日:2022-10-06
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Boon Bing Ng , James Michael Gardner , Scott A. Linn
CPC classification number: B41J2/04536 , B41J2/0458 , B41J2/04541 , B41J2/04555 , B41J2/04563 , B41J2/04586 , G06F3/1293 , G06F13/1668 , G11C7/1069 , G11C16/10 , G11C16/26 , G11C2207/105
Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component. The memory circuit includes a controllable selector connected in line with one of the signal paths via the I/O pads, the selector controllable to disconnect the corresponding signal path to the print component, and a memory component to store memory values associated with the print component. A control circuit, in response to a sequence of operating signals received by the I/O pads representing a memory read, to operate the controllable selector to disconnect the signal path to the print component to block the memory read of the print component, and provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.
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公开(公告)号:US20230150258A1
公开(公告)日:2023-05-18
申请号:US18099517
申请日:2023-01-20
Applicant: Hewlett-Packard Development Company, L.P.
Inventor: Boon Bing Ng , Mohan Kumar Sudhakar
IPC: B41J2/045
CPC classification number: B41J2/0455 , B41J2/04541 , B41J2/04586
Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes an ID line, a fire line, a discharge path, a memory element, and a latch. The memory element is electrically coupled to the fire line and the discharge path. The latch disables the discharge path in response to a first logic level on the ID line and enables the discharge path in response to a second logic level on the ID line.
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公开(公告)号:US11642883B2
公开(公告)日:2023-05-09
申请号:US17806332
申请日:2022-06-10
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Boon Bing Ng , Rui Pan , Mohan Kumar Sudhakar , Brendan Hall
CPC classification number: B41J2/0455 , B41J2/0458 , B41J2/04521 , B41J2/04541 , B41J2/04581 , B41J2/01 , B41J2/0452 , B41J2202/17
Abstract: In some examples, a circuit includes a data line, an input line, a first memory element, and a decoder to receive an address and to enable the first memory element for access in response to the address. The selector is responsive to the data line to select the first memory element, where the selector is to select the first memory element responsive to the data line having a first value, and where the data line is to communicate data of a second memory element in response to the second memory element being enabled for access. The input line is to communicate data of the first memory element in response to the first memory element being selected by the selector.
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公开(公告)号:US11518177B2
公开(公告)日:2022-12-06
申请号:US17223239
申请日:2021-04-06
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Boon Bing Ng , Noorashekin Binte Jamil
Abstract: The present subject matter relates to disposing memory banks and select register. In an example implementation, a plurality of memory banks is arranged to form a group of memory banks. Each memory bank includes a plurality of memory units. At least one select register generates a select signal to access the memory units in the plurality of memory banks. The at least one select register is disposed at an end of the group of memory banks.
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公开(公告)号:US11485133B2
公开(公告)日:2022-11-01
申请号:US16959077
申请日:2019-04-19
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor: Boon Bing Ng
Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a fire line, a plurality of memory elements, a first switch, and a plurality of second switches. The first switch is electrically coupled between the fire line and a first side of each memory element of the plurality of memory elements. Each second switch is electrically coupled to a second side of a respective memory element of the plurality of memory elements.
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