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公开(公告)号：US11806999B2
公开(公告)日：2023-11-07
申请号：US18045258
申请日：2022-10-10
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Boon Bing Ng , Erik D. Ness , James Michael Gardner
IPC: B41J2/045
CPC classification number: B41J2/04541 , B41J2/04586
Abstract: In some examples, a fluid dispensing device component includes a plurality of fluidic dies each comprising a memory, a plurality of control inputs to provide respective control information to respective fluidic dies of the plurality of fluidic dies, and a data bus connected to the plurality of fluidic dies, the data bus to provide data of the memories of the plurality of fluidic dies to an output of the fluid dispensing device component.
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公开(公告)号：US11787173B2
公开(公告)日：2023-10-17
申请号：US17884329
申请日：2022-08-09
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Boon Bing Ng , James Michael Gardner
IPC: B41J2/045
CPC classification number: B41J2/04541 , B41J2/04586
Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signals paths which communicate operating signals to the print component, and a memory component to store memory values associated with the print component. A control circuit to, in response to identifying a sequence of operating signals representing a memory read, provide a first analog signal on the analog pad in parallel with a second analog signal from the print component to provide an analog electrical value on the analog pad representing stored memory values selected by the memory read.
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公开(公告)号：US11498326B2
公开(公告)日：2022-11-15
申请号：US16768096
申请日：2019-07-31
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： James Michael Gardner , Boon Bing Ng
Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component. A memory component stores memory values associated with the print component, and a control circuit, in response to a sequence of operating signals on the I/O pads representing a memory read, provides an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.
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公开(公告)号：US11491782B2
公开(公告)日：2022-11-08
申请号：US16768541
申请日：2019-07-31
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Boon Bing Ng , James Michael Gardner , Scott A. Linn
Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component. The memory circuit includes a controllable selector connected in line with one of the signal paths via the I/O pads, the selector controllable to disconnect the corresponding signal path to the print component, and a memory component to store memory values associated with the print component. A control circuit, in response to a sequence of operating signals received by the I/O pads representing a memory read, to operate the controllable selector to disconnect the signal path to the print component to block the memory read of the print component, and provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.
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公开(公告)号：US20220314610A1
公开(公告)日：2022-10-06
申请号：US17847788
申请日：2022-06-23
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Boon Bing Ng
Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a plurality of first data lines, a second data line, a first memory element, and a second memory element. The first memory element is enabled in response to first data on the plurality of first data lines. The second memory element is enabled in response to second data on the second data line.
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Patent Agency Ranking
公开(公告)号：US10340011B2
公开(公告)日：2019-07-02
申请号：US15851413
申请日：2017-12-21
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Boon Bing Ng , Hang Ru Goy
IPC: G11C16/08 , G11C8/04 , G11C16/24 , G11C8/08 , G11C16/10 , G11C16/26 , H01L27/11514 , H01L29/423 , H01L29/78 , G11C8/12 , H01L27/11582
Abstract: Three-dimensional addressing for erasable programmable read only memory (EPROM) can include a number of EPROM banks, a number of shift registers, a row select data signal, a column select data signal, and a bank select data signal.
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公开(公告)号：US10014055B2
公开(公告)日：2018-07-03
申请号：US15327927
申请日：2014-07-30
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Boon Bing Ng , Thida Ma Win , Ning Ge , Jose Jehrome Rando
Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.
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公开(公告)号：US20180006045A1
公开(公告)日：2018-01-04
申请号：US15543355
申请日：2015-01-29
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Boon Bing Ng , Lui Cheat Thin , Reynaldo V Villavelez
IPC: H01L27/11517 , H01L29/788 , H01L29/423
CPC classification number: H01L27/11517 , H01L27/11521 , H01L29/40114 , H01L29/42324 , H01L29/42356 , H01L29/66825 , H01L29/7881
Abstract: The present subject matter relates to an electrical programmable read only memory (EPROM) cell. The EPROM cell comprises a semiconductor substrate and a floating gate separated from the semiconductor substrate by a first dielectric layer. A control gate is capacitively coupled to the floating gate through a second dielectric layer disposed between the floating gate and the control gate. In an example, the EPROM cell further comprises a conductive gate connected to the floating gate, wherein the conductive gate is to leak charges from the floating gate in a predetermined leak time period.
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公开(公告)号：US20170232743A1
公开(公告)日：2017-08-17
申请号：US15519310
申请日：2014-10-29
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Boon Bing Ng , Hang Ru Goy , Patrick Leonard , Shane O'Brien
CPC classification number: B41J2/14072 , B41J2/14153 , B41J2/1601 , B41J2/164 , B41J2/175 , B41J2202/18
Abstract: A fluid ejection device including a printhead die having a plurality of layers, including a single metal layer, and having an integrated ink level sensor. The ink level sensor includes an ink chamber above the metal layer, a metal plate of a sense capacitor disposed in the metal layer, and a clearing resistor circuit disposed in the metal layer including four clearing resistors arranged in a surround-4 configuration about the metal plate and electrically connected in parallel between a voltage potential and ground, wherein adjacent ends of at least two clearing resistors are not directly connected to one another so as to leave a gap between the adjacent ends in the metal layer. A metal lead in the metal layer extends through the gap to the metal plate.
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公开(公告)号：US20220314609A1
公开(公告)日：2022-10-06
申请号：US17847754
申请日：2022-06-23
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Boon Bing Ng
Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a plurality of first data lines, a second data line, a first memory element, and a second memory element. The first memory element is enabled in response to first data on the plurality of first data lines. The second memory element is enabled in response to second data on the second data line.
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