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公开(公告)号：US20100162199A1
公开(公告)日：2010-06-24
申请号：US12721343
申请日：2010-03-10
申请人： Peng Liu , Yu Cao , Luoqi Chen , Jun Ye
发明人： Peng Liu , Yu Cao , Luoqi Chen , Jun Ye
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/144 , G03F1/36 , G03F7/705 , G06F17/5009
摘要： A three-dimensional mask model of the invention provides a more realistic approximation of the three-dimensional effects of a photolithography mask with sub-wavelength features than a thin-mask model. In one embodiment, the three-dimensional mask model includes a set of filtering kernels in the spatial domain that are configured to be convolved with thin-mask transmission functions to produce a near-field image. In another embodiment, the three-dimensional mask model includes a set of correction factors in the frequency domain that are configured to be multiplied by the Fourier transform of thin-mask transmission functions to produce a near-field image.
摘要翻译： 本发明的三维掩模模型提供了比薄膜模型具有亚波长特征的光刻掩模的三维效果更逼真的近似。 在一个实施例中，三维掩模模型包括空间域中的一组过滤内核，其被配置为与薄膜传输函数进行卷积以产生近场图像。 在另一个实施例中，三维掩模模型包括频域中的一组校正因子，其被配置为乘以薄膜传输函数的傅立叶变换以产生近场图像。
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公开(公告)号：US20100122225A1
公开(公告)日：2010-05-13
申请号：US12613244
申请日：2009-11-05
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G03F1/14 , G03F1/44 , G03F1/68 , G03F7/70433 , G03F7/705 , G06F17/10 , G06F17/5009
摘要： The present invention relates generally to methods and apparatuses for test pattern selection for computational lithography model calibration. According to some aspects, the pattern selection algorithms of the present invention can be applied to any existing pool of candidate test patterns. According to some aspects, the present invention automatically selects those test patterns that are most effective in determining the optimal model parameter values from an existing pool of candidate test patterns, as opposed to designing optimal patterns. According to additional aspects, the selected set of test patterns according to the invention is able to excite all the known physics and chemistry in the model formulation, making sure that the wafer data for the test patterns can drive the model calibration to the optimal parameter values that realize the upper bound of prediction accuracy imposed by the model formulation.
摘要翻译： 本发明一般涉及用于计算光刻模型校准的测试图案选择的方法和装置。 根据一些方面，本发明的模式选择算法可以应用于任何现有的候选测试模式池。 根据一些方面，与设计最佳图案相反，本发明自动选择从现有的候选测试图案池中确定最佳模型参数值最有效的测试图案。 根据另外的方面，根据本发明的所选择的一组测试图案能够激发模型配方中的所有已知物理和化学，确保用于测试图案的晶片数据可以将模型校准驱动到最佳参数值 实现了模型公式对预测精度的上限。
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公开(公告)号：US07558419B1
公开(公告)日：2009-07-07
申请号：US10917060
申请日：2004-08-12
申请人： Jun Ye , Yu Cao , R. Fabian Pease
发明人： Jun Ye , Yu Cao , R. Fabian Pease
IPC分类号： G06K9/00
CPC分类号： G06T7/001 , G03F1/84 , G06T2207/30148
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for inspecting integrated circuits, including, for example, patterns projected, provided or formed on a wafer using photomasks, or patterns on the photomask itself. The inspection system and technique of this aspect includes first identifying, determining and/or detecting areas and/or patterns that are potentially defective by removing, filtering and/or eliminating from a set of potential defects any and/or all typical, regular or normal patterns. The identification, determination and/or detection of potential defects may be performed relatively quickly by a rapidly executing algorithm. In this way, a first or “coarse” analysis is performed rapidly and some, many, all or substantially all of the regular, normal or typical patterns are eliminated from further analysis. Thereafter, a second more detailed analysis is performed. This second analysis focuses on the set of potential defects that were identified, determined and/or detected during the first analysis of the photomask or wafer (i.e., the “coarse” analysis). The second analysis may be considerably a more detailed or a “fine” analysis relative to the first or “coarse” analysis. Indeed, in one embodiment, the second analysis may implement a more computational intensive process, without sacrificing throughput, since only a small portion of the photomask or wafer is inspected in the second analysis. In this way, the detailed analysis of the defect candidates may identify (i) all or substantially all of the actual defects and/or (ii) only the actual defects from the potential defects identified during the first analysis.
摘要翻译： 这里描述和说明了许多发明。 在一个方面，本发明涉及用于检查集成电路的技术和系统，包括例如使用光掩模投影，提供或形成在晶片上的图案或光掩模本身上的图案。 该方面的检查系统和技术包括首先识别，确定和/或检测潜在缺陷的区域和/或图案，该区域和/或图案通过去除，过滤和/或从一组潜在的缺陷中消除任何和/或所有典型的，规则的或正常的 模式。 可能通过快速执行的算法相对较快地执行潜在缺陷的识别，确定和/或检测。 以这种方式，快速执行第一个或“粗略”分析，并从进一步的分析中消除一些，许多，全部或基本上所有常规，正常或典型的模式。 此后，进行第二更详细的分析。 该第二分析集中在在光掩模或晶片的第一次分析期间（即，“粗略”分析））中识别，确定和/或检测到的潜在缺陷集合。 第二次分析可能相对于第一次或“粗略”分析可能是更详细或“精细”的分析。 实际上，在一个实施例中，第二分析可以实现更加计算密集的过程，而不会牺牲吞吐量，因为在第二次分析中只检查了一小部分光掩模或晶片。 以这种方式，缺陷候选人的详细分析可以识别（i）所有或基本上所有的实际缺陷和/或（ii）仅在第一次分析期间识别的潜在缺陷的实际缺陷。
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公开(公告)号：US20090053628A1
公开(公告)日：2009-02-26
申请号：US11892407
申请日：2007-08-22
IPC分类号： G03F7/20
CPC分类号： G03F7/705 , G03F7/70125 , G03F7/70458 , G03F7/70516 , G03F7/70525
摘要： A model-based tuning method for tuning a first lithography system utilizing a reference lithography system, each of which has tunable parameters for controlling imaging performance. The method includes the steps of defining a test pattern and an imaging model; imaging the test pattern utilizing the reference lithography system and measuring the imaging results; imaging the test pattern utilizing the first lithography system and measuring the imaging results; calibrating the imaging model utilizing the imaging results corresponding to the reference lithography system, where the calibrated imaging model has a first set of parameter values; tuning the calibrated imaging model utilizing the imaging results corresponding to the first lithography system, where the tuned calibrated model has a second set of parameter values; and adjusting the parameters of the first lithography system based on a difference between the first set of parameter values and the second set of parameter values.
摘要翻译： 一种基于模型的调谐方法，用于利用参考光刻系统调整第一光刻系统，每个参考光刻系统具有用于控制成像性能的可调参数。 该方法包括定义测试图案和成像模型的步骤; 使用参考光刻系统成像测试图案并测量成像结果; 使用第一光刻系统成像测试图案并测量成像结果; 使用对应于参考光刻系统的成像结果校准成像模型，其中校准的成像模型具有第一组参数值; 使用对应于第一光刻系统的成像结果来调整校准的成像模型，其中调谐的校准模型具有第二组参数值; 以及基于第一组参数值和第二组参数值之间的差异来调整第一光刻系统的参数。
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公开(公告)号：US20070022402A1
公开(公告)日：2007-01-25
申请号：US11527010
申请日：2006-09-26
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
摘要翻译： 这里描述和说明了许多发明。 在一个方面，本发明涉及用于模拟，验证，检查，表征，确定和/或评估光刻设计，技术和/或系统的技术和系统，和/或由其执行的各个功能或使用的组件 其中。 在一个实施例中，本发明是加速光刻特性和/或性质的光刻模拟，检查，表征和/或评估以及光刻系统和处理技术的效果和/或相互作用的系统和方法。 在这方面，在一个实施例中，本发明采用光刻仿真系统架构，包括特定于应用的硬件加速器，以及用于加速和促进掩模设计的验证，表征和/或检验的处理技术，例如RET设计 ，包括对整个光刻工艺进行详细的仿真和表征，以验证设计在最终的晶片图案上实现和/或提供期望的结果。 该系统包括：（1）通用目的型计算设备，用于执行在数据处理中具有分支和相互依赖性的基于案例的逻辑，以及（2）加速器子系统执行大部分计算密集型任务。
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公开(公告)号：US07120895B2
公开(公告)日：2006-10-10
申请号：US11084484
申请日：2005-03-18
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
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公开(公告)号：US07117477B2
公开(公告)日：2006-10-03
申请号：US11024121
申请日：2004-12-28
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
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公开(公告)号：US07114145B2
公开(公告)日：2006-09-26
申请号：US10989972
申请日：2004-11-16
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
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公开(公告)号：US20050166174A1
公开(公告)日：2005-07-28
申请号：US11084484
申请日：2005-03-18
申请人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
发明人： Jun Ye , Yen-Wen Lu , Yu Cao , Luoqi Chen , Xun Chen
CPC分类号： G06F17/5009 , G03F1/00 , G03F7/004 , G03F7/705 , G03F7/70666 , G06F17/5081 , G06F19/00 , G06F2217/12 , G06F2217/14 , G06T7/0004 , G06T2207/30148 , G21K5/00
摘要： There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
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60.发明授权公开(公告)号：US06782199B1
公开(公告)日：2004-08-24
申请号：US09696187
申请日：2000-10-26
申请人： Jun Ye , Yen-Wen Lu , Yu Cao
发明人： Jun Ye , Yen-Wen Lu , Yu Cao
IPC分类号： H04B1008
CPC分类号： H04B10/0793
摘要： Optical communications networks are provided that allow network maintainers to monitor or control subsystems using communications links other than optical telemetry links. The communications links may be wireless links or may be based on any other suitable communications links such as links using Ethernet cables or telephone lines. Network subsystems may be provided that include communications circuitry for communicating over the communications links. A network maintainer may use network control and management software implemented on computer equipment at a different location than the subsystems to communicate with the subsystems over the communications links. Because the communications links may function independently from the optical telemetry channels in the network, new subsystems may be added to the network without disturbing the existing network management software or telemetry arrangement.
摘要翻译： 提供了光通信网络，其允许网络维护者使用除光学遥测链路之外的通信链路监视或控制子系统。 通信链路可以是无线链路，或者可以基于任何其它合适的通信链路，例如使用以太网电缆或电话线的链路。 可以提供包括用于通过通信链路进行通信的通信电路的网络子系统。 网络维护者可以使用在与子系统不同的位置上在计算机设备上实现的网络控制和管理软件，以通过通信链路与子系统进行通信。 由于通信链路可以独立于网络中的光学遥测信道工作，所以可以将新的子系统添加到网络中，而不会干扰现有的网络管理软件或遥测装置。
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