公开(公告)号：US20130119634A1

公开(公告)日：2013-05-16

申请号：US13594654

申请日：2012-08-24

申请人： David Camp ,  Jose Gonzalez

发明人： David Camp ,  Jose Gonzalez

IPC分类号： B62J1/08

CPC分类号： B62J1/08 ,  B62J2001/085 ,  B62K19/00 ,  B62K19/36 ,  Y10T403/32237

摘要： An apparatus including an upper post, a main post, a control tube, a tension spring, and a hydraulic reset. The upper post can include a compression spring. The main post can be configured to telescopically mate with the upper post. The control tube can be rotably coupled to the main post. The tension spring can be configured to pull the upper post to the main post. The hydraulic reset can be configured to compress the compression spring. The upper post and the control tube can be configured to selectively lock the upper post to the control tube at at least two positions. In a first position of the control tube, the control tube can be configured to engage the compression spring. In a second position of the control tube, the control tube can be configured to disengage the compression spring.

摘要翻译： 一种包括上柱，主柱，控制管，拉伸弹簧和液压复位的装置。 上柱可包括压缩弹簧。 主柱可以配置为与顶柱可伸缩配合。 控制管可以可旋转地联接到主柱。 拉伸弹簧可以被配置成将上部支柱拉到主支柱。 液压复位可以配置成压缩压缩弹簧。 上柱和控制管可以构造成在至少两个位置选择性地将上柱固定到控制管。 在控制管的第一位置中，控制管可以被配置成接合压缩弹簧。 在控制管的第二位置，控制管可以被构造成使压缩弹簧脱离。

公开(公告)号：US08423716B2

公开(公告)日：2013-04-16

申请号：US13184424

申请日：2011-07-15

申请人： Fernando LaTorre ,  Jose Gonzalez ,  Antonio Gonzalez

发明人： Fernando LaTorre ,  Jose Gonzalez ,  Antonio Gonzalez

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F3/00

CPC分类号： G06F1/32 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3891

摘要： A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a plurality of back-end units, and an interconnect network to couple the front-end and back-end units. A method may include measuring a performance metric of a back-end unit, comparing the measurement to a first value, and reassigning, or not, the back-end unit according to the comparison. Computer systems according to embodiments of the invention may include: a random access memory; a system bus; and a processor having a plurality of instruction caches, a plurality of front-end units each to process an individual thread from a corresponding one of the instruction caches; a plurality of back-end units; and an interconnect network coupled to the plurality of front-end units and the plurality of back-end units.

公开(公告)号：US08251626B1

公开(公告)日：2012-08-28

申请号：US12579336

申请日：2009-10-14

申请人： Jose Gonzalez ,  Luis Figarella

发明人： Jose Gonzalez ,  Luis Figarella

IPC分类号： F16B19/00 ,  F16B21/00

CPC分类号： F16B13/02 ,  E01F9/553 ,  F16B9/02 ,  F16B11/006 ,  F16B13/0866 ,  F16B17/006 ,  F16B21/086

摘要： A bolt and receiver are provided to securely attach a device (e.g. light reflector or a lane marker) to a surface (such as a roadway). In addition to initially attaching the device to the surface, the bolt will nest progressively within the receiver as the surface thickness erodes or deteriorates over time, thus reducing the bolt's effective overall length (and thus the bolt's height above the surface), in order not to protrude and puncture or damage tires.

摘要翻译： 提供螺栓和接收器以将设备（例如，光反射器或车道标记）牢固地附接到表面（例如道路）上。 除了最初将装置附接到表面之外，随着表面厚度随着时间的推移侵蚀或劣化，螺栓将在接收器内逐渐嵌套，从而减少螺栓的有效总长度（从而降低螺栓在表面上方的高度），从而不会 突出并刺穿或损坏轮胎。

公开(公告)号：US07996617B2

公开(公告)日：2011-08-09

申请号：US12351780

申请日：2009-01-09

申请人： Fernando Latorre ,  Jose Gonzalez ,  Antonio Gonzalez

发明人： Fernando Latorre ,  Jose Gonzalez ,  Antonio Gonzalez

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F3/00

CPC分类号： G06F1/32 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3891

摘要： A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a plurality of back-end units, and an interconnect network to couple the front-end and back-end units. A method may include measuring a performance metric of a back-end unit, comparing the measurement to a first value, and reassigning, or not, the back-end unit according to the comparison. Computer systems according to embodiments of the invention may include: a random access memory; a system bus; and a processor having a plurality of instruction caches, a plurality of front-end units each to process an individual thread from a corresponding one of the instruction caches; a plurality of back-end units; and an interconnect network coupled to the plurality of front-end units and the plurality of back-end units.

摘要翻译： 提出了具有动态后端分配的多线程集群微架构。 处理系统可以包括多个指令高速缓存和前端单元，每个指令高速缓存和前端单元各自处理来自指令高速缓存中的相应一个的单独线程，多个后端单元和互连网络以耦合前端和后端 -end单位。 方法可以包括测量后端单元的性能度量，将测量与第一值进行比较，以及根据比较重新分配或不再分配后端单元。 根据本发明的实施例的计算机系统可以包括：随机存取存储器; 系统总线 以及具有多个指令高速缓存的处理器，多个前端单元，每个前端单元各自处理来自所述指令高速缓存中的相应一个的各个线程; 多个后端单元; 以及耦合到所述多个前端单元和所述多个后端单元的互连网络。

公开(公告)号：US20110134137A1

公开(公告)日：2011-06-09

申请号：US12633062

申请日：2009-12-08

申请人： Victor W. Lee ,  Mikhail Smelyanskiy ,  Ganesh S. Dasika ,  Jose Gonzalez ,  Jatin Chhugani ,  Yen-Kuang Chen ,  Changkyu Kim ,  Julio Gago ,  Santiago Galan ,  Victor Moya Del Barrio

发明人： Victor W. Lee ,  Mikhail Smelyanskiy ,  Ganesh S. Dasika ,  Jose Gonzalez ,  Jatin Chhugani ,  Yen-Kuang Chen ,  Changkyu Kim ,  Julio Gago ,  Santiago Galan ,  Victor Moya Del Barrio

IPC分类号： G09G5/00

CPC分类号： G06T11/001 ,  G06F17/16 ,  G06T1/00

摘要： A texture unit may be used utilized to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations.

摘要翻译： 可以使用纹理单元来执行诸如点积的通用数学计算。 这使得一些通用计算和操作能够从中央处理单元卸载到纹理单元。 纹理单元可以使用线性内插器来执行点积计算。

公开(公告)号：US07904533B1

公开(公告)日：2011-03-08

申请号：US11551704

申请日：2006-10-21

申请人： Jose Gonzalez ,  David Ham ,  Shane Lobo ,  Steve Parrott ,  Jonathan Rubin ,  Drew Shinholster ,  Todd Szymanski

发明人： Jose Gonzalez ,  David Ham ,  Shane Lobo ,  Steve Parrott ,  Jonathan Rubin ,  Drew Shinholster ,  Todd Szymanski

IPC分类号： G06F15/177

CPC分类号： H04L41/507 ,  H04L41/0853

摘要： A system having an integrated network and customer database is provided. The system retrieves router configurations to create the integrated database, which includes port data for each port on each router in each network. The system may determine the impact of proposed actions on routers. The system may process network events to display the status, port data, and customer data for each port. The system may respond to user input by polling a router and displaying the real time status, port data, and customer data for each port on the router.

摘要翻译： 提供具有集成网络和客户数据库的系统。 系统检索路由器配置以创建集成数据库，其中包括每个网络中每个路由器上每个端口的端口数据。 系统可以确定提出的动作对路由器的影响。 系统可以处理网络事件以显示每个端口的状态，端口数据和客户数据。 系统可以通过轮询路由器并显示路由器上每个端口的实时状态，端口数据和客户数据来响应用户输入。

公开(公告)号：US07814322B2

公开(公告)日：2010-10-12

申请号：US11381326

申请日：2006-05-02

申请人： David Gurevich ,  Jose Gonzalez ,  Scott Burke

发明人： David Gurevich ,  Jose Gonzalez ,  Scott Burke

IPC分类号： H04L9/32

CPC分类号： H04W8/005 ,  H04L45/20 ,  H04L45/26 ,  H04L63/061 ,  H04L63/0823 ,  H04L63/162 ,  H04W12/04 ,  H04W12/06 ,  H04W40/246 ,  H04W84/18 ,  H04W88/06

摘要： Wireless network devices discover individual mesh nodes and networks of mesh nodes. An association is formed on the basis of peer-to-peer interactions at layer-1, layer-2 and/or higher layers of the Open System Interconnect (OSI) model. In particular, the system uses Beacon, Probe Request, Probe Response, Association Request, Association Response, and Disassociation frames and introduces a new Extensible Mesh Information Element (EMIE) used by mesh nodes to discover, authenticate, and associate with other peer nodes.

摘要翻译： 无线网络设备发现网格节点的网格节点和网络。 基于开放系统互连（OSI）模型的第1层，第2层和/或更高层的对等交互形成关联。 特别地，该系统使用信标，探测请求，探测响应，关联请求，关联响应和解除关联帧，并引入了由网状节点使用的新的可扩展网状信息元素（EMIE）来发现，认证和与其他对等节点相关联。

公开(公告)号：US07698512B2

公开(公告)日：2010-04-13

申请号：US11827904

申请日：2007-07-13

申请人： Grigorios Magklis ,  Jose Gonzalez ,  Pedro Chaparro ,  Qiong Cai ,  Antonio Gonzalez

发明人： Grigorios Magklis ,  Jose Gonzalez ,  Pedro Chaparro ,  Qiong Cai ,  Antonio Gonzalez

IPC分类号： G06F12/00

CPC分类号： G06F12/084 ,  G06F12/0833 ,  Y02D10/13

摘要： In one embodiment, the present invention includes a method for determining if data of a memory request by a first agent is in a memory region represented by a region indicator of a region table of the first agent, and transmitting a compressed address for the memory request to other agents of a system if the memory region is represented by the region indicator, otherwise transmitting a full address. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种方法，用于确定由第一代理的存储器请求的数据是否在由第一代理的区域表的区域指示符表示的存储器区域中，并且发送用于存储器请求的压缩地址 如果存储器区域由区域指示符表示，则传送到系统的其它代理，否则发送完整地址。 描述和要求保护其他实施例。

公开(公告)号：US07665000B2

公开(公告)日：2010-02-16

申请号：US11714938

申请日：2007-03-07

申请人： Antonio Gonzalez ,  Qiong Cai ,  Jose Gonzalez ,  Pedro Chaparro ,  Grigorios Magklis ,  Ryan Rakvic

发明人： Antonio Gonzalez ,  Qiong Cai ,  Jose Gonzalez ,  Pedro Chaparro ,  Grigorios Magklis ,  Ryan Rakvic

IPC分类号： G01R31/28

CPC分类号： G06F9/52 ,  G06F11/3404 ,  G06F11/3495

摘要： An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. The embodiment may also include logic to periodically identify which thread in a set of threads is a critical thread. The critical thread may be the slowest thread and criticality may be determined by examining meeting point counts. The embodiment may also include logic to selectively manipulate a configurable attribute of the critical thread and/or core upon which the critical thread will run.

摘要翻译： 提供了一种基于在会议点处理期间收集的信息来识别关键线程的装置。 设备的一个实施例可以包括用于在确定它们已经到达会议点时选择性地更新线程的会议点计数的逻辑。 该实施例还可以包括用于周期性地识别一组线程中的哪个线程是关键线程的逻辑。 关键线程可能是最慢的线程，可以通过检查会议点数来确定关键性。 该实施例还可以包括选择性地操纵关键线程和/或核心的可配置属性的逻辑，关键线程将在其上运行。

公开(公告)号：US07657766B2

公开(公告)日：2010-02-02

申请号：US11698612

申请日：2007-01-26

申请人： Jose Gonzalez ,  Antonio Gonzalez

发明人： Jose Gonzalez ,  Antonio Gonzalez

IPC分类号： G06F1/32

CPC分类号： G06F9/3885 ,  G06F9/3891

摘要： In some embodiments, an apparatus for an energy efficient clustered micro-architecture are disclosed. In one embodiment, the micro-architecture computes an energy delay2 product for each active instruction scheduler and one or more associated function blocks of a current architecture configuration over a predetermined period. Once the energy delay2 product is computed, the computed product is compared against an energy delay2 product calculated for a prior architecture configuration to determine an effectiveness (energy efficiency) of the current architecture configuration. Based on the effectiveness of the current architecture configuration, a number of active instruction schedulers and one or more associated functional blocks within the current architecture configuration is adjusted. In one embodiment, the number of active instruction schedulers and one or more associated functional blocks may be increased or decreased to improve power efficiency of the cluster micro-architecture. Other embodiments are described and claimed.

摘要翻译： 在一些实施例中，公开了一种用于能量效率的集群微架构的装置。 在一个实施例中，微架构在预定时段内为每个活动指令调度器和当前体系结构配置的一个或多个相关功能块计算能量延迟2乘积。 一旦计算了energy delay2产品，将计算的产品与针对先前架构配置计算的能量延迟2乘积进行比较，以确定当前架构配置的有效性（能效）。 基于当前架构配置的有效性，调整当前架构配置中的多个主动指令调度器和一个或多个相关联的功能块。 在一个实施例中，可以增加或减少活动指令调度器和一个或多个相关联的功能块的数量，以提高集群微架构的功率效率。 描述和要求保护其他实施例。