利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

113 条记录 (耗时 0.03 秒)

    Multithreaded clustered microarchitecture with dynamic back-end assignment
    1.
    发明授权
    Multithreaded clustered microarchitecture with dynamic back-end assignment 失效

    公开(公告)号：US08423716B2

    公开(公告)日：2013-04-16

    申请号：US13184424

    申请日：2011-07-15

    申请人： Fernando LaTorre ,  Jose Gonzalez ,  Antonio Gonzalez

    发明人： Fernando LaTorre ,  Jose Gonzalez ,  Antonio Gonzalez

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F3/00

    CPC分类号： G06F1/32 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3891

    摘要： A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a plurality of back-end units, and an interconnect network to couple the front-end and back-end units. A method may include measuring a performance metric of a back-end unit, comparing the measurement to a first value, and reassigning, or not, the back-end unit according to the comparison. Computer systems according to embodiments of the invention may include: a random access memory; a system bus; and a processor having a plurality of instruction caches, a plurality of front-end units each to process an individual thread from a corresponding one of the instruction caches; a plurality of back-end units; and an interconnect network coupled to the plurality of front-end units and the plurality of back-end units.

    Multithreaded clustered microarchitecture with dynamic back-end assignment
    2.
    发明授权
    Multithreaded clustered microarchitecture with dynamic back-end assignment 有权
    具有动态后端分配的多线程集群微架构

    公开(公告)号：US07996617B2

    公开(公告)日：2011-08-09

    申请号：US12351780

    申请日：2009-01-09

    申请人： Fernando Latorre ,  Jose Gonzalez ,  Antonio Gonzalez

    发明人： Fernando Latorre ,  Jose Gonzalez ,  Antonio Gonzalez

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F3/00

    CPC分类号： G06F1/32 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3891

    摘要： A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a plurality of back-end units, and an interconnect network to couple the front-end and back-end units. A method may include measuring a performance metric of a back-end unit, comparing the measurement to a first value, and reassigning, or not, the back-end unit according to the comparison. Computer systems according to embodiments of the invention may include: a random access memory; a system bus; and a processor having a plurality of instruction caches, a plurality of front-end units each to process an individual thread from a corresponding one of the instruction caches; a plurality of back-end units; and an interconnect network coupled to the plurality of front-end units and the plurality of back-end units.

    摘要翻译： 提出了具有动态后端分配的多线程集群微架构。 处理系统可以包括多个指令高速缓存和前端单元，每个指令高速缓存和前端单元各自处理来自指令高速缓存中的相应一个的单独线程，多个后端单元和互连网络以耦合前端和后端 -end单位。 方法可以包括测量后端单元的性能度量，将测量与第一值进行比较，以及根据比较重新分配或不再分配后端单元。 根据本发明的实施例的计算机系统可以包括：随机存取存储器; 系统总线 以及具有多个指令高速缓存的处理器，多个前端单元，每个前端单元各自处理来自所述指令高速缓存中的相应一个的各个线程; 多个后端单元; 以及耦合到所述多个前端单元和所述多个后端单元的互连网络。

    Compressing address communications between processors
    3.
    发明授权
    Compressing address communications between processors 有权
    压缩处理器之间的地址通信

    公开(公告)号：US07698512B2

    公开(公告)日：2010-04-13

    申请号：US11827904

    申请日：2007-07-13

    申请人： Grigorios Magklis ,  Jose Gonzalez ,  Pedro Chaparro ,  Qiong Cai ,  Antonio Gonzalez

    发明人： Grigorios Magklis ,  Jose Gonzalez ,  Pedro Chaparro ,  Qiong Cai ,  Antonio Gonzalez

    IPC分类号： G06F12/00

    CPC分类号： G06F12/084 ,  G06F12/0833 ,  Y02D10/13

    摘要： In one embodiment, the present invention includes a method for determining if data of a memory request by a first agent is in a memory region represented by a region indicator of a region table of the first agent, and transmitting a compressed address for the memory request to other agents of a system if the memory region is represented by the region indicator, otherwise transmitting a full address. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括一种方法，用于确定由第一代理的存储器请求的数据是否在由第一代理的区域表的区域指示符表示的存储器区域中，并且发送用于存储器请求的压缩地址 如果存储器区域由区域指示符表示，则传送到系统的其它代理，否则发送完整地址。 描述和要求保护其他实施例。

    Meeting point thread characterization
    4.
    发明授权
    Meeting point thread characterization 有权
    汇点线程表征

    公开(公告)号：US07665000B2

    公开(公告)日：2010-02-16

    申请号：US11714938

    申请日：2007-03-07

    申请人： Antonio Gonzalez ,  Qiong Cai ,  Jose Gonzalez ,  Pedro Chaparro ,  Grigorios Magklis ,  Ryan Rakvic

    发明人： Antonio Gonzalez ,  Qiong Cai ,  Jose Gonzalez ,  Pedro Chaparro ,  Grigorios Magklis ,  Ryan Rakvic

    IPC分类号： G01R31/28

    CPC分类号： G06F9/52 ,  G06F11/3404 ,  G06F11/3495

    摘要： An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. The embodiment may also include logic to periodically identify which thread in a set of threads is a critical thread. The critical thread may be the slowest thread and criticality may be determined by examining meeting point counts. The embodiment may also include logic to selectively manipulate a configurable attribute of the critical thread and/or core upon which the critical thread will run.

    摘要翻译： 提供了一种基于在会议点处理期间收集的信息来识别关键线程的装置。 设备的一个实施例可以包括用于在确定它们已经到达会议点时选择性地更新线程的会议点计数的逻辑。 该实施例还可以包括用于周期性地识别一组线程中的哪个线程是关键线程的逻辑。 关键线程可能是最慢的线程，可以通过检查会议点数来确定关键性。 该实施例还可以包括选择性地操纵关键线程和/或核心的可配置属性的逻辑，关键线程将在其上运行。

    Apparatus for an energy efficient clustered micro-architecture
    5.
    发明授权
    Apparatus for an energy efficient clustered micro-architecture 失效
    用于能量效率的集群微架构的装置

    公开(公告)号：US07657766B2

    公开(公告)日：2010-02-02

    申请号：US11698612

    申请日：2007-01-26

    申请人： Jose Gonzalez ,  Antonio Gonzalez

    发明人： Jose Gonzalez ,  Antonio Gonzalez

    IPC分类号： G06F1/32

    CPC分类号： G06F9/3885 ,  G06F9/3891

    摘要： In some embodiments, an apparatus for an energy efficient clustered micro-architecture are disclosed. In one embodiment, the micro-architecture computes an energy delay2 product for each active instruction scheduler and one or more associated function blocks of a current architecture configuration over a predetermined period. Once the energy delay2 product is computed, the computed product is compared against an energy delay2 product calculated for a prior architecture configuration to determine an effectiveness (energy efficiency) of the current architecture configuration. Based on the effectiveness of the current architecture configuration, a number of active instruction schedulers and one or more associated functional blocks within the current architecture configuration is adjusted. In one embodiment, the number of active instruction schedulers and one or more associated functional blocks may be increased or decreased to improve power efficiency of the cluster micro-architecture. Other embodiments are described and claimed.

    摘要翻译： 在一些实施例中，公开了一种用于能量效率的集群微架构的装置。 在一个实施例中，微架构在预定时段内为每个活动指令调度器和当前体系结构配置的一个或多个相关功能块计算能量延迟2乘积。 一旦计算了energy delay2产品，将计算的产品与针对先前架构配置计算的能量延迟2乘积进行比较，以确定当前架构配置的有效性（能效）。 基于当前架构配置的有效性，调整当前架构配置中的多个主动指令调度器和一个或多个相关联的功能块。 在一个实施例中，可以增加或减少活动指令调度器和一个或多个相关联的功能块的数量，以提高集群微架构的功率效率。 描述和要求保护其他实施例。