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公开(公告)号：US07665000B2
公开(公告)日：2010-02-16
申请号：US11714938
申请日：2007-03-07
申请人： Antonio Gonzalez , Qiong Cai , Jose Gonzalez , Pedro Chaparro , Grigorios Magklis , Ryan Rakvic
发明人： Antonio Gonzalez , Qiong Cai , Jose Gonzalez , Pedro Chaparro , Grigorios Magklis , Ryan Rakvic
IPC分类号： G01R31/28
CPC分类号： G06F9/52 , G06F11/3404 , G06F11/3495
摘要： An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. The embodiment may also include logic to periodically identify which thread in a set of threads is a critical thread. The critical thread may be the slowest thread and criticality may be determined by examining meeting point counts. The embodiment may also include logic to selectively manipulate a configurable attribute of the critical thread and/or core upon which the critical thread will run.
摘要翻译： 提供了一种基于在会议点处理期间收集的信息来识别关键线程的装置。 设备的一个实施例可以包括用于在确定它们已经到达会议点时选择性地更新线程的会议点计数的逻辑。 该实施例还可以包括用于周期性地识别一组线程中的哪个线程是关键线程的逻辑。 关键线程可能是最慢的线程，可以通过检查会议点数来确定关键性。 该实施例还可以包括选择性地操纵关键线程和/或核心的可配置属性的逻辑，关键线程将在其上运行。
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公开(公告)号：US20080222466A1
公开(公告)日：2008-09-11
申请号：US11714938
申请日：2007-03-07
申请人： Antonio Gonzalez , Qiong Cai , Jose Gonzalez , Pedro Chaparro , Grigorios Magklis , Ryan Rakvic
发明人： Antonio Gonzalez , Qiong Cai , Jose Gonzalez , Pedro Chaparro , Grigorios Magklis , Ryan Rakvic
IPC分类号： G01R31/28
CPC分类号： G06F9/52 , G06F11/3404 , G06F11/3495
摘要： An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. The embodiment may also include logic to periodically identify which thread in a set of threads is a critical thread. The critical thread may be the slowest thread and criticality may be determined by examining meeting point counts. The embodiment may also include logic to selectively manipulate a configurable attribute of the critical thread and/or core upon which the critical thread will run.
摘要翻译： 提供了一种基于在会议点处理期间收集的信息来识别关键线程的装置。 设备的一个实施例可以包括用于在确定它们已经到达会议点时选择性地更新线程的会议点计数的逻辑。 该实施例还可以包括用于周期性地识别一组线程中的哪个线程是关键线程的逻辑。 关键线程可能是最慢的线程，临界点可以通过检查会议点数来确定。 该实施例还可以包括选择性地操纵关键线程和/或核心的可配置属性的逻辑，关键线程将在其上运行。
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公开(公告)号：US07698512B2
公开(公告)日：2010-04-13
申请号：US11827904
申请日：2007-07-13
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0833 , Y02D10/13
摘要： In one embodiment, the present invention includes a method for determining if data of a memory request by a first agent is in a memory region represented by a region indicator of a region table of the first agent, and transmitting a compressed address for the memory request to other agents of a system if the memory region is represented by the region indicator, otherwise transmitting a full address. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种方法，用于确定由第一代理的存储器请求的数据是否在由第一代理的区域表的区域指示符表示的存储器区域中，并且发送用于存储器请求的压缩地址 如果存储器区域由区域指示符表示，则传送到系统的其它代理，否则发送完整地址。 描述和要求保护其他实施例。
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4.发明申请THREAD MIGRATION TO IMPROVE POWER EFFICIENCY IN A PARALLEL PROCESSING ENVIRONMENT 有权螺旋式移动以提高平行处理环境中的功率效率公开(公告)号：US20090172424A1
公开(公告)日：2009-07-02
申请号：US11968060
申请日：2007-12-31
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/329 , G06F1/3296 , G06F9/4893 , Y02D10/126 , Y02D10/172 , Y02D10/24
摘要： A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads.
摘要翻译： 一种选择性地移动由多个处理核并行执行的多个线程中的一个或多个的方法和系统。 在一个实施例中，可以将线程从执行多个处理核心中的一个移动到在多个处理核心中的另一个处理核心中执行，基于与多个线程相关联的性能特性来移动线程。 在本发明的另一实施例中，可以改变多个处理核心的功率状态，以提高与执行多个线程相关联的功率效率。
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公开(公告)号：US20090019219A1
公开(公告)日：2009-01-15
申请号：US11827904
申请日：2007-07-13
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0833 , Y02D10/13
摘要： In one embodiment, the present invention includes a method for determining if data of a memory request by a first agent is in a memory region represented by a region indicator of a region table of the first agent, and transmitting a compressed address for the memory request to other agents of a system if the memory region is represented by the region indicator, otherwise transmitting a full address. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种方法，用于确定由第一代理的存储器请求的数据是否在由第一代理的区域表的区域指示符表示的存储器区域中，并且发送用于存储器请求的压缩地址 如果存储器区域由区域指示符表示，则传送到系统的其它代理，否则发送完整地址。 描述和要求保护其他实施例。
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公开(公告)号：US20080244278A1
公开(公告)日：2008-10-02
申请号：US10594827
申请日：2006-06-30
CPC分类号： G01R31/025
摘要： Methods and apparatus to provide leakage power estimation are described. In one embodiment, one or more sensed temperature values (108) and one or more voltage values (110) are utilized to determine the leakage power of an integrated circuit (IC) component. Other embodiments are also described.
摘要翻译： 描述提供泄漏功率估计的方法和装置。 在一个实施例中，利用一个或多个感测温度值（108）和一个或多个电压值（110）来确定集成电路（IC）组件的泄漏功率。 还描述了其它实施例。
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公开(公告)号：US07814339B2
公开(公告)日：2010-10-12
申请号：US10594827
申请日：2006-06-30
CPC分类号： G01R31/025
摘要： Methods and apparatus to provide leakage power estimation are described. In one embodiment, one or more sensed temperature values (108) and one or more voltage values (110) are utilized to determine the leakage power of an integrated circuit (IC) component. Other embodiments are also described.
摘要翻译： 描述提供泄漏功率估计的方法和装置。 在一个实施例中，利用一个或多个感测温度值（108）和一个或多个电压值（110）来确定集成电路（IC）组件的泄漏功率。 还描述了其它实施例。
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公开(公告)号：US20130173948A1
公开(公告)日：2013-07-04
申请号：US13780023
申请日：2013-02-28
IPC分类号： G06F1/06
CPC分类号： G06F1/06 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F9/3869 , Y02D10/126 , Y02D10/172
摘要： A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.
摘要翻译： 一种用于缩放微处理器的至少一个时钟域的频率和工作电压的方法和装置。 更具体地，本发明的实施例涉及将微处理器划分为时钟域并且独立于其他时钟域来控制每个时钟域的频率和工作电压的技术。
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公开(公告)号：US20060117202A1
公开(公告)日：2006-06-01
申请号：US10999786
申请日：2004-11-29
IPC分类号： G06F1/12
CPC分类号： G06F1/06 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F9/3869 , Y02D10/126 , Y02D10/172
摘要： A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.
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公开(公告)号：US20140164802A1
公开(公告)日：2014-06-12
申请号：US14181999
申请日：2014-02-17
IPC分类号： G06F1/32
CPC分类号： G06F1/06 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F9/3869 , Y02D10/126 , Y02D10/172
摘要： A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.
摘要翻译： 一种用于缩放微处理器的至少一个时钟域的频率和工作电压的方法和装置。 更具体地，本发明的实施例涉及将微处理器划分为时钟域并且独立于其他时钟域来控制每个时钟域的频率和工作电压的技术。
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