公开(公告)号：US11710684B2

公开(公告)日：2023-07-25

申请号：US17070427

申请日：2020-10-14

Applicant: Infineon Technologies AG

Inventor： Frank Singer ,  Martin Gruber ,  Thorsten Meyer ,  Thorsten Scharf ,  Peter Strobel ,  Stefan Woetzel

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L21/54 ,  H01L23/16

CPC classification number: H01L23/49575 ,  H01L21/54 ,  H01L21/56 ,  H01L23/16 ,  H01L23/31 ,  H01L23/49541

Abstract: A package is disclosed. In one example, the package comprises a substrate having at least one first recess on a front side and at least one second recess on a back side, wherein the substrate is separated into a plurality of separate substrate sections by the at least one first recess and the at least one second recess, an electronic component mounted on the front side of the substrate, and a single encapsulant filling at least part of the at least one first recess and at least part of the at least one second recess. The encapsulant fully circumferentially surrounds sidewalls of at least one of the substrate sections.

公开(公告)号：US20230178428A1

公开(公告)日：2023-06-08

申请号：US17543199

申请日：2021-12-06

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Fee Hoon Wendy Wong ,  Thomas Behrens ,  Eric Lopez Bonifacio ,  Chau Fatt Chiang ,  Irmgard Escher-Poeppel ,  Giovanni Ragasa Garbin ,  Martin Gruber ,  Tien Shyang Law ,  Mohamad Azian Mohamed Azizi ,  Si Hao Vincent Yeo

IPC: H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L21/76838 ,  H01L21/563 ,  H01L23/31 ,  H01L21/4839

Abstract: A method includes providing a lead frame with a central metal plate and a plurality of leads extending away from the central metal plate, the central metal plate including an upper surface that includes a first mesa that is elevated from recessed regions, mounting a semiconductor die on the upper surface of central metal plate such that a lower surface of the semiconductor die is at least partially disposed on the first mesa, forming electrical interconnections between terminals of the semiconductor die and the leads, forming an encapsulant body on the central metal plate such that the semiconductor die is encapsulated by the encapsulant body and such that the leads protrude out from edge sides of the encapsulant body, and thinning the central metal plate from a rear surface of the central metal plate so as to isolate the first mesa at a lower surface of the encapsulant body.

公开(公告)号：US20210111108A1

公开(公告)日：2021-04-15

申请号：US17070427

申请日：2020-10-14

Applicant: Infineon Technologies AG

Inventor： Frank Singer ,  Martin Gruber ,  Thorsten Meyer ,  Thorsten Scharf ,  Peter Strobel ,  Stefan Woetzel

IPC: H01L23/495 ,  H01L23/16 ,  H01L23/31 ,  H01L21/54 ,  H01L21/56

Abstract: A package is disclosed. In one example, the package comprises a substrate having at least one first recess on a front side and at least one second recess on a back side, wherein the substrate is separated into a plurality of separate substrate sections by the at least one first recess and the at least one second recess, an electronic component mounted on the front side of the substrate, and a single encapsulant filling at least part of the at least one first recess and at least part of the at least one second recess. The encapsulant fully circumferentially surrounds sidewalls of at least one of the substrate sections.

公开(公告)号：US10964628B2

公开(公告)日：2021-03-30

申请号：US16282207

申请日：2019-02-21

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Martin Gruber ,  Josef Hoeglauer ,  Michael Juerss ,  Josef Maerz ,  Thorsten Meyer ,  Bun Kian Tay

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

公开(公告)号：US20210043603A1

公开(公告)日：2021-02-11

申请号：US17078460

申请日：2020-10-23

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Stephan Bradl ,  Stefan Miethaner ,  Alexander Heinrich ,  Horst Theuss ,  Peter Scherl

IPC: H01L23/00 ,  H01L23/495 ,  H01L21/677 ,  H01L21/56 ,  H01L21/67 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31

Abstract: A method of forming a semiconductor package includes providing a panel, providing one or more metal layers on an upper surface of the panel, forming a die pad and bond pads from the one or more metal layers, the die pad being adjacent to and spaced apart from the bond pads, attaching a die to the die pad, forming electrical connections between the die and the bond pads, encapsulating the die and the electrical connections with an electrically insulating mold compound, removing portions of the panel, and exposing the die pad and the bond pads after encapsulating the die.

公开(公告)号：US10700037B2

公开(公告)日：2020-06-30

申请号：US15811375

申请日：2017-11-13

Applicant: Infineon Technologies AG

Inventor： Eung San Cho ,  Thorsten Meyer ,  Xaver Schloegel ,  Thomas Behrens ,  Josef Hoeglauer

IPC: H01L23/00 ,  H01L23/498

Abstract: In some examples, a device includes a semiconductor element, a layer element, and a single connector element electrically connecting the semiconductor element and the layer element. In some examples, the single connector element includes two or more discrete connector elements, and each discrete connector element of the two or more discrete connector elements electrically connects the semiconductor element and the layer element. In some examples, the single connector element also includes conductive material attached to the two or more discrete connector elements.

公开(公告)号：US10566309B2

公开(公告)日：2020-02-18

申请号：US15284580

申请日：2016-10-04

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Peter Scherl ,  Stephan Bradl ,  Stefan Miethaner ,  Alexander Heinrich ,  Horst Theuss

IPC: H01L21/48 ,  H01L21/78 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

Abstract: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel. A second packaging substrate panel is provided. The first and second packaging substrate panels are moved through an assembly line that includes a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The second type packaged semiconductor device is different than the first type packaged semiconductor device. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner.

公开(公告)号：US20190157449A1

公开(公告)日：2019-05-23

申请号：US16235550

申请日：2018-12-28

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andreas Meiser ,  Hans-Peter Lang ,  Thorsten Meyer ,  Peter Irsigler

IPC: H01L29/78 ,  H01L23/48 ,  H01L27/06 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L21/74 ,  H01L29/66 ,  H01L29/45 ,  H01L29/861 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/423

Abstract: A semiconductor device includes a semiconductor body includes a first side and a second side opposite to the first side, a first dielectric disposed on the first side, a second dielectric disposed on the second side, one or more FET devices disposed at the first side, a first contact trench extending through the first dielectric at the first side, a first conductive material disposed in the first contact trench and electrically connected to the semiconductor body, a second contact trench extending through the second dielectric and into the semiconductor body at the second side, and a second conductive material disposed in the second contact trench and electrically connected to the semiconductor body at sidewalls of the second contact trench.

公开(公告)号：US10168391B2

公开(公告)日：2019-01-01

申请号：US15049923

申请日：2016-02-22

Applicant: Infineon Technologies AG

Inventor： Giuliano Angelo Babulano ,  Jens Oetjen ,  Liu Chen ,  Toni Salminen ,  Stefan Mieslinger ,  Markus Dinkel ,  Martin Gruber ,  Franz Jost ,  Thorsten Meyer ,  Rainer Schaller

IPC: H01L25/16 ,  G01R33/00 ,  G01R33/09 ,  H01L43/08 ,  H01L43/02

Abstract: An interconnect module includes a metal clip having a first end section, a second end section and a middle section extending between the first and the second end sections. The first end section is configured for external attachment to a bare semiconductor die or packaged semiconductor die attached to a carrier or to a metal region of the carrier. The second end section is configured for external attachment to a different metal region of the carrier or to a different semiconductor die or packaged semiconductor die attached to the carrier. The module further includes a magnetic field sensor secured to the metal clip. The magnetic field sensor is operable to sense a magnetic field produced by current flowing through the metal clip. The interconnect module can be used to form a direct electrical connection between components and/or metal regions of a carrier to which the module is attached.

公开(公告)号：US10043768B2

公开(公告)日：2018-08-07

申请号：US14709648

申请日：2015-05-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Thorsten Meyer ,  Ludwig Heitzer

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31

Abstract: A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line.