公开(公告)号：US12158448B2

公开(公告)日：2024-12-03

申请号：US18050178

申请日：2022-10-27

Applicant: Infineon Technologies AG

Inventor： Derek Debie ,  Klaus Elian ,  Ludwig Heitzer ,  David Tumpold ,  Jens Pohl ,  Cyrus Ghahremani ,  Thorsten Meyer ,  Christian Geissler ,  Andreas Allmeier

IPC: G01N29/22 ,  G01N25/00 ,  G01N29/02 ,  G01N29/24

Abstract: A radiation source device includes at least one membrane layer, a radiation source structure to emit electromagnetic or infrared radiation, a substrate and a spacer structure, wherein the substrate and the at least one membrane form a chamber, wherein a pressure in the chamber is lower than or equal to a pressure outside of the chamber, and wherein the radiation source structure is arranged between the at least one membrane layer and the substrate.

公开(公告)号：US11531056B2

公开(公告)日：2022-12-20

申请号：US16849931

申请日：2020-04-15

Applicant: Infineon Technologies AG

Inventor： Irmgard Escher-Poeppel ,  Thorsten Meyer ,  Gerhard Poeppel

IPC: G01R31/26 ,  G01R31/28 ,  G01R31/316 ,  H01L23/60

Abstract: The disclosure describes to techniques for detecting field failures or performance degradation of circuits, including integrated circuits (IC), by including additional contacts, i.e. terminals, along with the functional contacts that used for connecting the circuit to a system in which the circuit is a part. These additional contacts may be used to measure dynamic changing electrical characteristics over time e.g. voltage, current, temperature and impedance. These electrical characteristics may be representative of a certain failure mode and may be an indicator for circuit state-of-health (SOH), while the circuit is performing in the field.

公开(公告)号：US20210325445A1

公开(公告)日：2021-10-21

申请号：US16849931

申请日：2020-04-15

Applicant: Infineon Technologies AG

Inventor： Irmgard Escher-Poeppel ,  Thorsten Meyer ,  Gerhard Poeppel

IPC: G01R31/26 ,  G01R31/28 ,  G01R31/316 ,  H01L23/60

Abstract: The disclosure describes to techniques for detecting field failures or performance degradation of circuits, including integrated circuits (IC), by including additional contacts, i.e. terminals, along with the functional contacts that used for connecting the circuit to a system in which the circuit is a part. These additional contacts may be used to measure dynamic changing electrical characteristics over time e.g. voltage, current, temperature and impedance. These electrical characteristics may be representative of a certain failure mode and may be an indicator for circuit state-of-health (SOH), while the circuit is performing in the field.

公开(公告)号：US20210005557A1

公开(公告)日：2021-01-07

申请号：US16917947

申请日：2020-07-01

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Thomas Behrens ,  Martin Gruber ,  Thorsten Scharf ,  Peter Strobel

IPC: H01L23/544 ,  H01L23/00

Abstract: A method of mounting electronic components on one or more carrier bodies is disclosed. The method comprises providing a support body with at least one first alignment mark, mounting the one or more carrier bodies, each having at least one second alignment mark, on the support body by alignment between the at least one first alignment mark and the at least one second alignment mark. Thereafter, the method includes mounting the plurality of electronic components on a respective one of the one or more carrier bodies by alignment using the at least one second alignment mark.

公开(公告)号：US20200273781A1

公开(公告)日：2020-08-27

申请号：US16282207

申请日：2019-02-21

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Martin Gruber ,  Josef Hoeglauer ,  Michael Juerss ,  Josef Maerz ,  Thorsten Meyer ,  Bun Kian Tay

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

公开(公告)号：US10734352B2

公开(公告)日：2020-08-04

申请号：US16148316

申请日：2018-10-01

Applicant: Infineon Technologies AG

Inventor： Irmgard Escher-Poeppel ,  Khalil Hosseini ,  Johannes Lodermeyer ,  Joachim Mahler ,  Thorsten Meyer ,  Georg Meyer-Berg ,  Ivan Nikitin ,  Reinhard Pufall ,  Edmund Riedl ,  Klaus Schmidt ,  Manfred Schneegans ,  Patrick Schwarz

IPC: H01L23/00

Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.

公开(公告)号：US20200021002A1

公开(公告)日：2020-01-16

申请号：US16032589

申请日：2018-07-11

Applicant: Infineon Technologies AG

Inventor： Maciej Wojnowski ,  Dirk Hammerschmidt ,  Walter Hartner ,  Johannes Lodermeyer ,  Chiara Mariotti ,  Thorsten Meyer

IPC: H01P3/16 ,  H01L23/66 ,  H01Q3/44

Abstract: A semiconductor device including an Integrated Circuit (IC) package and a plastic waveguide. The IC package includes a semiconductor chip; and an embedded antenna formed within a Redistribution Layer (RDL) coupled to the semiconductor chip, wherein the RDL is configured to transport a Radio Frequency (RF) signal between the semiconductor chip and the embedded antenna. The plastic waveguide is attached to the IC package and configured to transport the RF signal between the embedded antenna and outside of the IC package.

公开(公告)号：US20190221531A1

公开(公告)日：2019-07-18

申请号：US16360387

申请日：2019-03-21

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Walter Hartner ,  Maciej Wojnowski

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/522 ,  H01Q1/22 ,  H01L29/06 ,  H01L23/00

CPC classification number: H01L23/66 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5226 ,  H01L23/5227 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L29/0657 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01Q1/2283 ,  H01L2924/00014

Abstract: A semiconductor device includes a semiconductor die having an active main surface and an opposite main surface opposite the active main surface. The semiconductor device further includes an antenna arranged on the active main surface of the semiconductor die and a recess arranged on the opposite main surface of the semiconductor die. The recess is arranged over the antenna.

公开(公告)号：US10354925B2

公开(公告)日：2019-07-16

申请号：US15278164

申请日：2016-09-28

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Werner Schwetlick

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L21/28 ,  H01L29/78 ,  H01L29/40 ,  H01L21/8238

Abstract: A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface, first trenches and second trenches extending from the first surface into the semiconductor body, at least one lateral IGFET including a first load terminal at the first surface, a second load terminal at the first surface and a gate electrode within the first trenches, and at least one vertical IGFET including a first load terminal at the first surface, a second load terminal at the second surface and a gate electrode within the second trenches. The first trenches extend from the first surface into the semiconductor body deeper than a channel zone of the lateral IGFET and confine the channel zone.

公开(公告)号：US09984900B2

公开(公告)日：2018-05-29

申请号：US15226260

申请日：2016-08-02

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Jens Pohl

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/488 ,  H01L23/00 ,  H01L23/498 ,  H01L21/683 ,  H01L21/78 ,  H01L23/28 ,  H01L23/50 ,  H01L23/538

CPC classification number: H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/28 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/488 ,  H01L23/49861 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/14 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05099

Abstract: A semiconductor device includes a chip, at least one element electrically coupled to the chip, an adhesive at least partially covering the at least one element, and a mold material at least partially covering the chip and the adhesive.