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公开(公告)号:US11302668B2
公开(公告)日:2022-04-12
申请号:US16720867
申请日:2019-12-19
发明人: Thorsten Meyer , Gerald Ofner , Stephan Bradl , Stefan Miethaner , Alexander Heinrich , Horst Theuss , Peter Scherl
IPC分类号: H01L21/677 , H01L21/56 , H01L21/67 , H01L21/48 , H01L21/78 , H01L23/00 , H01L23/495 , H01L23/31
摘要: A method of producing packaged semiconductor devices includes providing a first packaging substrate panel, providing a second packaging substrate panel, and moving the first and second packaging substrate panels through an assembly line that comprises a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner. The first and second packaged semiconductor devices differ with respect to at least one of: lead configuration, and encapsulant configuration.
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公开(公告)号:US10930614B2
公开(公告)日:2021-02-23
申请号:US15659670
申请日:2017-07-26
发明人: Manfred Mengel , Alexander Heinrich , Steffen Orso , Thomas Behrens , Oliver Eichinger , Lim Fong , Evelyn Napetschnig , Edmund Riedl
IPC分类号: H01L23/00 , B23K35/30 , B23K35/26 , B23K35/28 , C22C13/00 , C22C18/00 , C22C18/04 , C22C30/04 , C22C30/06 , H01L23/488 , H01L23/495 , B23K1/00
摘要: A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.
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公开(公告)号:US20200219841A1
公开(公告)日:2020-07-09
申请号:US16820069
申请日:2020-03-16
发明人: Edmund Riedl , Wu Hu Li , Alexander Heinrich , Ralf Otremba , Werner Reiss
摘要: A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.
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公开(公告)号:US20190006311A1
公开(公告)日:2019-01-03
申请号:US16126190
申请日:2018-09-10
发明人: Alexander Heinrich , Michael Juerss , Konrad Roesl , Oliver Eichinger , Kok Chai Goh , Tobias Schmidt
IPC分类号: H01L23/00 , H01L29/45 , H01L29/43 , H01L23/482 , H01L23/495
CPC分类号: H01L24/32 , H01L23/4827 , H01L23/49513 , H01L23/49541 , H01L23/49582 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/29 , H01L24/83 , H01L29/43 , H01L29/45 , H01L2224/03438 , H01L2224/0345 , H01L2224/04026 , H01L2224/05083 , H01L2224/05124 , H01L2224/05139 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05669 , H01L2224/08503 , H01L2224/2745 , H01L2224/29082 , H01L2224/29084 , H01L2224/291 , H01L2224/29101 , H01L2224/29105 , H01L2224/29109 , H01L2224/29111 , H01L2224/29113 , H01L2224/29118 , H01L2224/29124 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29166 , H01L2224/29169 , H01L2224/29171 , H01L2224/29184 , H01L2224/32225 , H01L2224/32245 , H01L2224/32503 , H01L2224/32507 , H01L2224/83191 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/8346 , H01L2224/83464 , H01L2224/83469 , H01L2224/83815 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01047 , H01L2924/01048 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/1461 , H01L2924/17738 , H01L2924/17747 , H01L2924/1776 , H01L2924/00014 , H01L2924/01023 , H01L2924/01015 , H01L2924/00
摘要: A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer.
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公开(公告)号:US10014275B2
公开(公告)日:2018-07-03
申请号:US15459151
申请日:2017-03-15
发明人: Alexander Heinrich , Irmgard Escher-Poeppel , Martin Gruber , Andreas Munding , Catharina Wille
CPC分类号: H01L24/81 , H01L24/09 , H01L24/16 , H01L24/85 , H01L25/50 , H01L2224/095 , H01L2224/16104 , H01L2224/16112 , H01L2224/16137 , H01L2224/48091 , H01L2224/48472 , H01L2224/49113 , H01L2224/4912 , H01L2924/00014 , H01L2224/45099
摘要: One aspect of the invention relates to a method for producing a chip assemblage. Two or more chip assemblies are produced in each case by cohesively and electrically conductively connecting an electrically conductive first compensation lamina to a first main electrode of a semiconductor chip. A control electrode interconnection structure is arranged in a free space between the chip assemblies. Electrically conductive connections are produced between the control electrode interconnection structure and control electrodes of the semiconductor chips of the individual chip assemblies. The chip assemblies are cohesively connected by means of a dielectric embedding compound.
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公开(公告)号:US09756726B2
公开(公告)日:2017-09-05
申请号:US14071296
申请日:2013-11-04
CPC分类号: H05K1/11 , H01L24/45 , H01L24/46 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/45015 , H01L2224/45028 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/45184 , H01L2224/4554 , H01L2224/48091 , H01L2224/48092 , H01L2224/48137 , H01L2224/48227 , H01L2224/48465 , H01L2224/48507 , H01L2224/48511 , H01L2224/85 , H01L2224/85181 , H01L2224/85205 , H01L2224/85207 , H01L2924/00014 , H01L2924/13055 , H01L2924/181 , H05K1/111 , H05K1/14 , H05K3/32 , H05K3/36 , H05K3/4015 , H05K2201/04 , H05K2203/0285 , Y10T29/49126 , H01L2924/00 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/00012 , H01L2224/48247 , H01L2224/43 , H01L2224/85399 , H01L2224/05599
摘要: An electronic device may comprise a semiconductor element and a wire bond connecting the semiconductor element to a substrate. Using a woven bonding wire may improve the mechanical and electrical properties of the wire bond. Furthermore, there may be a cost benefit. Woven bonding wires may be used in any electronic device, for example in power devices or integrated logic devices.
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公开(公告)号:US20170025375A1
公开(公告)日:2017-01-26
申请号:US15282927
申请日:2016-09-30
发明人: Alexander Heinrich , Michael Juerss , Konrad Roesl , Oliver Eichinger , Kok Chai Goh , Tobias Schmidt
IPC分类号: H01L23/00 , H01L23/495
CPC分类号: H01L24/32 , H01L23/4827 , H01L23/49513 , H01L23/49541 , H01L23/49582 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/29 , H01L24/83 , H01L29/43 , H01L29/45 , H01L2224/03438 , H01L2224/0345 , H01L2224/04026 , H01L2224/05083 , H01L2224/05124 , H01L2224/05139 , H01L2224/05166 , H01L2224/05171 , H01L2224/05184 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05669 , H01L2224/08503 , H01L2224/2745 , H01L2224/29082 , H01L2224/29084 , H01L2224/291 , H01L2224/29101 , H01L2224/29105 , H01L2224/29109 , H01L2224/29111 , H01L2224/29113 , H01L2224/29118 , H01L2224/29124 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29166 , H01L2224/29169 , H01L2224/29171 , H01L2224/29184 , H01L2224/32225 , H01L2224/32245 , H01L2224/32503 , H01L2224/32507 , H01L2224/83191 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/8346 , H01L2224/83464 , H01L2224/83469 , H01L2224/83815 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01047 , H01L2924/01048 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/1461 , H01L2924/17738 , H01L2924/17747 , H01L2924/1776 , H01L2924/00014 , H01L2924/01023 , H01L2924/01015 , H01L2924/00
摘要: An electric device with a multi-layer contact is disclosed. In an embodiment, the electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.
摘要翻译: 公开了具有多层接触的电气设备。 在一个实施例中,电子设备包括载体,连接到载体的半导体衬底以及设置在半导体衬底和载体之间的层系统。 层系统包括设置在半导体衬底上的电接触层。 功能层设置在电接触层上。 粘附层设置在功能层上。 在粘合层和载体之间设置焊料层。
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公开(公告)号:US20140167224A1
公开(公告)日:2014-06-19
申请号:US13715922
申请日:2012-12-14
IPC分类号: H01L23/48 , H01L21/768
CPC分类号: H01L21/78 , H01L21/6836 , H01L23/3677 , H01L24/27 , H01L24/29 , H01L24/83 , H01L29/0657 , H01L29/45 , H01L2221/68327 , H01L2224/29101 , H01L2224/2929 , H01L2224/293 , H01L2224/83191 , H01L2224/83365 , H01L2224/8382 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/1461 , H01L2924/00 , H01L2924/014 , H01L2924/00014
摘要: A semiconductor device includes a semiconductor chip including a first main face and a second main face. The second main face is the backside of the semiconductor chip. The second main face includes a first region and a second region. The second region is a peripheral region of the second main face and the level of the first region and the level of the second region are different. The first region may be filled with metal and may be planarized to the same level as the second region.
摘要翻译: 半导体器件包括具有第一主面和第二主面的半导体芯片。 第二主面是半导体芯片的背面。 第二主面包括第一区域和第二区域。 第二区域是第二主面的周边区域,第一区域的高度和第二区域的高度不同。 第一区域可以用金属填充,并且可以被平坦化到与第二区域相同的水平。
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公开(公告)号:US20230126663A1
公开(公告)日:2023-04-27
申请号:US18088238
申请日:2022-12-23
摘要: A layer structure includes a first layer including at least one material selected from a first group consisting of nickel, copper, gold, silver, palladium, tin, zinc, platinum, and an alloy of any of these materials; a third layer including at least one material selected from a second group consisting of nickel, copper, gold, palladium, tin, silver, zinc, platinum, and an alloy of any of these materials; and a second layer between the first layer and the third layer. The second layer consists of or essentially consists of nickel and tin. The second layer includes an intermetallic phase of nickel and tin.
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公开(公告)号:US10896893B2
公开(公告)日:2021-01-19
申请号:US16820069
申请日:2020-03-16
发明人: Edmund Riedl , Wu Hu Li , Alexander Heinrich , Ralf Otremba , Werner Reiss
IPC分类号: H01L23/00 , H01L23/498 , B23K1/00 , B23K1/20 , B23K35/26 , B23K35/28 , B23K101/38
摘要: A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.
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