公开(公告)号：US10831679B2

公开(公告)日：2020-11-10

申请号：US15934916

申请日：2018-03-23

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Joseph Nuzman ,  Baiju Patel

IPC: G06F12/14 ,  G06F12/02 ,  G06F21/52

Abstract: Systems, methods, and apparatuses for defending against cross-privilege linear access are described. For example, an implementation of an apparatus comprising privilege level storage to store a current privilege level and address check circuitry coupled to the privilege level storage, wherein the address check circuitry is to determine whether a linear address associated with an instruction is allowed to access a partition of a linear address space of the apparatus based upon a comparison of the current privilege level and a most significant bit of the linear address is described.

公开(公告)号：US20180137053A1

公开(公告)日：2018-05-17

申请号：US15352272

申请日：2016-11-15

Applicant: INTEL CORPORATION

Inventor： Pavel I. Kryukov ,  Stanislav Shwartsman ,  Joseph Nuzman ,  Alexandr Titov

IPC: G06F12/0808 ,  G06F12/0811 ,  G06F12/0837 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891

CPC classification number: G06F12/0808 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0837 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0891 ,  G06F2212/1016 ,  G06F2212/1041 ,  G06F2212/502 ,  G06F2212/6042

Abstract: An example system on a chip (SoC) includes a cache, a processor, and a predictor circuit. The cache may store data. The processor may be coupled to the cache and store a first data set at a first location in the cache and receive a first request from an application to write a second data set to the cache. The predictor circuit may be coupled to the processor and determine that a second location where the second data set is to be written to in the cache is nonconsecutive to the first location, where the processor is to perform a request-for-ownership (RFO) operation for the second data set and write the second data set to the cache.

公开(公告)号：US09766968B2

公开(公告)日：2017-09-19

申请号：US14668862

申请日：2015-03-25

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ady Tal ,  Ron Gabor ,  Joseph Nuzman

IPC: G06F11/07 ,  G06F11/10

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/10 ,  G06F11/1064

Abstract: Memory corruption detection technologies are described. A processor can include a memory to store data from an application, wherein the memory comprises a memory corruption detection (MCD) table. The processor can also include processor core coupled to the memory. The processor core can receive, from an application, a memory access request to access data of one or more contiguous memory blocks in a memory object of the memory. The processor core can also retrieve data stored in the one or more contiguous memory blocks based on the location indicated by the pointer. The processor core can also retrieve, from the MCD table, allocation information associated with the one or more contiguous memory blocks. The processor core can also send, to the application, a fault message when a fault event associated with the retrieved data occurs based on the allocation information.

公开(公告)号：US09727475B2

公开(公告)日：2017-08-08

申请号：US14497740

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Ishwar Agarwal ,  Yen-Cheng Liu ,  Joseph Nuzman ,  Ashok Jagannathan ,  Bahaa Fahim ,  Nithiyanandan Bashyam

IPC: G06F12/00 ,  G06F12/0875 ,  G06F12/0831

CPC classification number: G06F12/0875 ,  G06F12/0831 ,  G06F2212/452

Abstract: An apparatus and method are described for distributed snoop filtering. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions and process data; first snoop logic to track a first plurality of cache lines stored in a mid-level cache (“MLC”) accessible by one or more of the cores, the first snoop logic to allocate entries for cache lines stored in the MLC and to deallocate entries for cache lines evicted from the MLC, wherein at least some of the cache lines evicted from the MLC are retained in a level 1 (L1) cache; and second snoop logic to track a second plurality of cache lines stored in a non-inclusive last level cache (NI LLC), the second snoop logic to allocate entries in the NI LLC for cache lines evicted from the MLC and to deallocate entries for cache lines stored in the MLC, wherein the second snoop logic is to store and maintain a first set of core valid bits to identify cores containing copies of the cache lines stored in the NI LLC.

公开(公告)号：US20160371139A1

公开(公告)日：2016-12-22

申请号：US14745172

申请日：2015-06-19

Applicant: Intel Corporation

Inventor： Tomer Stark ,  Ron Gabor ,  Ady Tal ,  Joseph Nuzman

IPC: G06F11/07 ,  G06F11/16

CPC classification number: G06F12/1425 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0766 ,  G06F11/0772 ,  G06F11/0787 ,  G06F11/1666 ,  G06F12/0238 ,  G06F2201/80 ,  G06F2212/1032

Abstract: Memory corruption detection technologies are described. A processing system can include a processor core including a register to store an address of a memory corruption detection (MCD) table. The processor core can receive, from an application, a memory store request to store data in a first portion of a contiguous memory block of the memory object of a memory. The memory store request comprises a first pointer indicating a first location of the first portion in the memory block to store the data. The processor core can retrieve, from the MCD table, a write protection indicator that indicates a first protection mode of the first portion. The processor core can send, to the application, a fault message when a fault event associated with the first portion occurs based on the first protection mode of the first portion.

Abstract translation: 描述了内存损坏检测技术。 处理系统可以包括处理器核心，其包括用于存储存储器破坏检测（MCD）表的地址的寄存器。 处理器核心可以从应用程序接收存储器存储请求，以将数据存储在存储器的存储器对象的连续存储器块的第一部分中。 存储器存储请求包括指示存储器块中的第一部分的第一位置以存储数据的第一指针。 处理器核心可以从MCD表中检索指示第一部分的第一保护模式的写保护指示符。 当基于第一部分的第一保护模式发生与第一部分相关联的故障事件时，处理器核心可以向应用发送故障消息。

公开(公告)号：US20160342515A1

公开(公告)日：2016-11-24

申请号：US15162707

申请日：2016-05-24

Applicant: Intel Corporation

Inventor： Larisa Novakovsky ,  Joseph Nuzman ,  Alexander Gendler

IPC: G06F12/0811 ,  G06F12/0831

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0831 ,  G06F12/0837 ,  G06F12/0891 ,  G06F2212/283 ,  G06F2212/621

Abstract: A method for determining an inclusion policy includes determining a ratio of a capacity of a large cache to a capacity of a core cache in a cache subsystem of a processor and selecting an inclusive policy as the inclusion policy for the cache subsystem in response to the cache ratio exceeding an inclusion threshold. The method may further include selecting a non-inclusive policy in response to the cache ratio not exceeding the inclusion threshold and, responsive to a cache transaction resulting in a cache miss, performing an inclusion operation that invokes the inclusion policy.

Abstract translation: 用于确定包含策略的方法包括确定大型缓存的容量与处理器的高速缓存子系统中的核心高速缓存的容量的比率，并且选择包含策略作为响应于高速缓存的高速缓存子系统的包含策略 比例超过包含阈值。 该方法还可以包括响应于不超过包含阈值的高速缓存比率选择不包含策略，并且响应于导致高速缓存未命中的高速缓存事务，执行调用包含策略的包含操作。

公开(公告)号：US09378148B2

公开(公告)日：2016-06-28

申请号：US13843315

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Larisa Novakovsky ,  Joseph Nuzman ,  Alexander Gendler

IPC: G06F12/0891 ,  G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0831 ,  G06F12/0837 ,  G06F12/0891 ,  G06F2212/283 ,  G06F2212/621

Abstract: A method for determining an inclusion policy includes determining a ratio of a capacity of a large cache to a capacity of a core cache in a cache subsystem of a processor and selecting an inclusive policy as the inclusion policy for the cache subsystem in response to the cache ratio exceeding an inclusion threshold. The method may further include selecting a non-inclusive policy in response to the cache ratio not exceeding the inclusion threshold and, responsive to a cache transaction resulting in a cache miss, performing an inclusion operation that invokes the inclusion policy.

Abstract translation: 用于确定包含策略的方法包括确定大型缓存的容量与处理器的高速缓存子系统中的核心高速缓存的容量的比率，并且选择包含策略作为响应于高速缓存的高速缓存子系统的包含策略 比例超过包含阈值。 该方法还可以包括响应于不超过包含阈值的高速缓存比率选择不包含策略，并且响应于导致高速缓存未命中的高速缓存事务，执行调用包含策略的包含操作。

公开(公告)号：US12271735B2

公开(公告)日：2025-04-08

申请号：US18419059

申请日：2024-01-22

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Raanan Sade ,  Liron Zur ,  Igor Yanover ,  Joseph Nuzman

IPC: G06F9/30 ,  G06F9/54 ,  G06F11/30 ,  G06F11/34

Abstract: Systems, methods, and apparatuses relating to circuitry to precisely monitor memory store accesses are described. In one embodiment, a system includes a memory, a hardware processor core comprising a decoder to decode an instruction into a decoded instruction, an execution circuit to execute the decoded instruction to produce a resultant, a store buffer, and a retirement circuit to retire the instruction when a store request for the resultant from the execution circuit is queued into the store buffer for storage into the memory, and a performance monitoring circuit to mark the retired instruction for monitoring of post-retirement performance information between being queued in the store buffer and being stored in the memory, enable a store fence after the retired instruction to be inserted that causes previous store requests to complete within the memory, and on detection of completion of the store request for the instruction in the memory, store the post-retirement performance information in storage of the performance monitoring circuit.

公开(公告)号：US20250053651A1

公开(公告)日：2025-02-13

申请号：US18925667

申请日：2024-10-24

Applicant: Intel Corporation

Inventor： Robert S. Chappell ,  Jared W. Stark, IV ,  Joseph Nuzman ,  Stephen Robinson ,  Jason W. Brandt

IPC: G06F21/55 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F12/0802 ,  G06F21/62

Abstract: Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor includes a core having a plurality of physical contexts to execute a plurality of threads, a plurality of structures shared by the plurality of threads, a context mapping structure to map context signatures to respective physical contexts of the plurality of physical contexts, each physical context to identify and differentiate state of the plurality of structures, and a context manager circuit to, when one or more of a plurality of fields that comprise a context signature is changed, search the context mapping structure for a match to another context signature, and when the match is found, a physical context associated with the match is set as an active physical context for the core.

公开(公告)号：US12130915B2

公开(公告)日：2024-10-29

申请号：US17590470

申请日：2022-02-01

Applicant: Intel Corporation

Inventor： Robert S. Chappell ,  Jared W. Stark, IV ,  Joseph Nuzman ,  Stephen Robinson ,  Jason W. Brandt

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F12/0802 ,  G06F21/55 ,  G06F21/62

CPC classification number: G06F21/556 ,  G06F9/30116 ,  G06F9/30123 ,  G06F9/30196 ,  G06F9/3806 ,  G06F9/3808 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/4881 ,  G06F12/0802 ,  G06F21/62

Abstract: Systems, methods, and apparatuses relating to microarchitectural mechanisms for the prevention of side-channel attacks are disclosed herein. In one embodiment, a processor core includes an instruction fetch circuit to fetch instructions; a branch target buffer comprising a plurality of entries that each include a thread identification (TID) and a privilege level bit; and a branch predictor, coupled to the instruction fetch circuit and the branch target buffer, to predict a target instruction corresponding to a branch instruction based on at least one entry of the plurality of entries in the branch target buffer, and cause the target instruction to be fetched by the instruction fetch circuit.